 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| march 2009 rev 2 1/193 st72321rx st72321arx st72321jx 64/44-pin 8-bit mcu with 32 to 60k flash/rom, adc, five timers, spi, sci, i 2 c interface features memories ? 32k to 60k dual voltage high density flash (hdflash) or rom with read-out protection capability. in-applic ation programming and in-circuit programmin g for hdflash devices ? 1k to 2k ram ? hdflash endurance: 100 cycles, data reten- tion: 40 years at 85c clock, reset and supply management ? enhanced low voltage supervisor (lvd) for main supply and auxiliar voltage detector (avd) with interr upt capability ? clock sources: crystal/ceramic resonator os- cillators, internal rc oscillator and bypass for external clock ? pll for 2x frequency multiplication ? four power saving modes: halt, active-halt, wait and slow interrupt management ? nested interrupt controller ? 14 interrupt vectors plus trap and reset ? top level interrupt (tli) pin on 64-pin devices ? 15/9 external interrupt lines (on 4 vectors) up to 48 i/o ports ? 48/32/24 multifunctional bidirectional i/o lines ? 34/22/17 alternate function lines ? 16/12/10 high sink outputs 5 timers ? main clock controller with: real time base, beep and clock-out capabilities ? configurable watchdog timer ? two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, pwm and pulse generator modes ? 8-bit pwm auto-reload timer with: 2 input cap- tures, 4 pwm outputs, output compare and time base interrupt, external clock with event detector 3 communications interfaces ? spi synchronous serial interface ? sci asynchronous serial interface ?i 2 c multimaster interface 1 analog peripheral ? 10-bit adc with up to 16 input ports instruction set ? 8-bit data manipulation ? 63 basic instructions ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction development tools ? full hardware/software development package ? in-circuit testing capability table 1. device summary lqfp64 10 x 10 lqfp64 14 x 14 lqfp44 10 x 10 lqfp32 7 x 7 features st72321r9/st72321ar9/ st72321j9 st72321r7/st72321ar7/ st72321j7 st72321r6/st72321ar6 program memory - bytes flash/rom 60k flash/rom 48k flash/rom 32k ram (stack) - bytes 2048 (256) 1536 (256) 1024 (256) operating voltage 3.8 to 5.5v temp. range -40 to +125c, -40 to +85c package lqfp64 14x14 (r), lqfp64 10x10 (ar), lqfp44 10x10 (j) 1
table of contents 193 2/193 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.4 internal low volt age detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.2 auxiliary voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.6.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 external interrupt control regi ster (eicr) . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1 table of contents 3/193 8.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4.1 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.5.1 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.4 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.1.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.6 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.7 using halt mode with the wdg (wdghalt option) . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.2 main clock controller with real time clock and beeper (mcc/rtc) . . 57 10.2.1 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.3 real time clock timer (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.4 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.2.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.2.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3 pwm auto-reload timer (art) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.4.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.4.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 1 table of contents 193 4/193 10.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.5.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.5.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.5.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.5.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.5.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.6 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.6.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.6.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.6.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.7 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 15 10.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.7.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.7.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.7.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.7.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.8 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 28 10.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.8.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.8.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 11.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table of contents 5/193 12.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . 141 12.3.3 auxiliary volt age detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.3.4 external voltage detector (evd) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.4.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.4.2 supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.4.3 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.1 general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.3 crystal and ceramic re sonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.5.4 rc oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.5.5 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.6.1 ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.6.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7.1 functional ems (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7.2 electro magnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.7.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 155 12.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.8.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.9.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.9.2 iccsel/vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.10timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.10.1 8-bit pwm-art auto-reload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.10.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 62 12.11communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 163 12.11.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.11.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.1210-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.12.1 analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12.12.2 general pcb design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12.12.3 adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 13 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14 st72321 device configuration and ordering information . . . . . . . . . . . . . . . 175 table of contents 193 6/193 14.1 flash option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.2 device ordering inform ation and transfer of customer code . . . . . 177 14.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3.1 starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3.2 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3.4 socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.1 all flash and rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.1.1 external rc option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.1.2 safe connection of osc1/osc2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.1.3 reset pin protection with lvd enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.1.4 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.1.5 external interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.1.6 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 187 15.1.7 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.1.8 16-bit timer pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.1.9 timd set simultaneously with oc interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.1.10 i2c multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.2 all flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.2.1 internal rc oscillator with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3 limitations specific to rev q and rev s fl ash devices . . . . . . . . . . . . . . . 189 15.3.1 adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.4 limitations specific to rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.4.1 lvd operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.4.2 lvd startup behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.3 avd not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.4 internal rc oscillator ope ration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.5 external clock source with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.6 pull-up not present on pe2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.7 read-out protection with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.4.8 safe connection of osc1/osc2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 st72321rx st72321arx st72321jx 7/193 1 description the st72f321 flash and st72321 rom devices are members of the st7 microcontroller family de- signed for mid-range applications. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set and are available with flash or rom pro- gram memory. the st7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. the on-chip peripherals include an a/d converter, a pwm autoreload timer, 2 general purpose tim- ers, i 2 c bus, spi interface and an sci interface. for power economy, microcontroller can switch dynamically into wait, slow, active-halt or halt mode when the application is in idle or stand-by state. typical applications are consumer, home, office and industrial products. related documentation an1131: migrating applications from st72511/ 311/314 to st72521/321/324 figure 1. device block diagram 8-bit core alu address and data bus osc1 v pp control program (32k - 60k bytes) v dd reset port f pf7:0 (8-bits) timer a beep port a ram (1024 - 2048 bytes) port c 10-bit adc v aref v ssa port b pb7:0 (8-bits) pwm art port e pe7:0 (8-bits) sci timer b pa7:0 (8-bits) port d pd7:0 (8-bits) spi pc7:0 (8-bits) v ss watchdog tli osc lvd osc2 memory mcc/rtc/beep evd avd i2c st72321rx st72321arx st72321jx 8/193 2 pin description figure 2. 64-pin lqfp 14x14 and 10x10 package pinout v aref v ssa v dd_3 v ss_3 mco / ain8 / pf0 beep / (hs) pf1 (hs) pf2 ocmp2_a / ain9 / pf3 ocmp1_a / ain10 / pf4 icap2_a / ain11 / pf5 icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain4 / pd4 ain5 / pd5 ain6 / pd6 ain7 / pd7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei3 ei0 ei1 pwm3 / pb0 pwm2 / pb1 pwm1 / pb2 pwm0 / pb3 artclk / (hs) pb4 artic1 / pb5 artic2 / pb6 pb7 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 (hs) pe4 (hs) pe5 (hs) pe6 (hs) pe7 pa1 pa0 pc7 / ss / ain15 pc6 / sck / iccclk pc5 / mosi / ain14 pc4 / miso / iccdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b / ain13 pc0 / ocmp2_b / ain12 v ss_0 v dd_0 v ss_1 v dd_1 pa3 (hs) pa2 v dd _2 osc1 osc2 v ss _2 tli evd reset v pp / iccsel pa7 (hs) / scli pa6 (hs) / sdai pa5 (hs) pa4 (hs) pe3 pe2 pe1 / rdi pe0 / tdo (hs) 20ma high sink capability eix associated external interrupt vector st72321rx st72321arx st72321jx 9/193 figure 3. 44-pin lqfp package pinout mco / ain8 / pf0 beep / (hs) pf1 (hs) pf2 ocmp1_a / ain10 / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v aref v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pb3 (hs) pb4 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 ain4 / pd4 rdi / pe1 pb0 pb1 pb2 pc6 / sck / iccclk pc5 / mosi / ain14 pc4 / miso / iccdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b / ain13 pc0 / ocmp2_b / ain12 v ss_1 v dd_1 pa3 (hs) pc7 / ss / ain15 v ss _2 reset v pp / iccsel pa7 (hs)/ scli pa6 (hs) / sdai pa5 (hs) pa4 (hs) pe0 / tdo v dd _2 osc1 osc2 eix associated external interrupt vector (hs) 20ma high sink capability st72321rx st72321arx st72321jx 10/193 pin description (cont?d) for external pin connection guidelines, refer to see ?electrical characteristics? on page 138. legend / abbreviations for table 2 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd c t = cmos 0.3v dd /0.7v dd with input trigger t t = ttl 0.8v / 2v with schmitt trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: ? input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog ? output: od = open drain 2) , pp = push-pull refer to ?i/o ports? on page 46 for more details on the software configuration of the i/o ports. the reset configuration of ea ch pin is shown in bold. th is configuration is valid as long as the device is in reset state. table 2. device pin description pin n pin name type level port main function (after reset) alternate function lqfp64 lqfp44 lqfp32 input output input output float wpu int ana od pp 1 - - pe4 (hs) i/o c t hs x xxxport e4 2 - - pe5 (hs) i/o c t hs x xxxport e5 3 - - pe6 (hs) i/o c t hs x xxxport e6 4 - - pe7 (hs) i/o c t hs x xxxport e7 5 2 28 pb0/pwm3 i/o c t x ei2 x x port b0 pwm output 3 6 3 - pb1/pwm2 i/o c t x ei2 x x port b1 pwm output 2 7 4 - pb2/pwm1 i/o c t x ei2 x x port b2 pwm output 1 8 5 29 pb3/pwm0 i/o c t x ei2 x x port b3 pwm output 0 9 6 30 pb4 (hs)/artclk i/o c t hs x ei3 x x port b4 pwm-art external clock 10 - - pb5 / artic1 i/o c t x ei3 x x port b5 pwm-art input capture 1 11 - - pb6 / artic2 i/o c t x ei3 x x port b6 pwm-art input capture 2 12 - - pb7 i/o c t x ei3 x x port b7 13 7 31 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 14 8 32 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 15 9 - pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 16 10 - pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 17 11 - pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 18 12 - pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 19 - - pd6/ain6 i/o c t x x x x x port d6 adc analog input 6 20 - - pd7/ain7 i/o c t x x x x x port d7 adc analog input 7 21 13 1 v aref i analog reference voltage for adc 22 14 2 v ssa s analog ground voltage st72321rx st72321arx st72321jx 11/193 23 - - v dd_3 s digital main supply voltage 24 - - v ss_3 s digital ground voltage 25 15 3 pf0/mco/ain8 i/o c t x ei1 x x x port f0 main clock out (f osc /2) adc ana- log input 8 26 16 4 pf1 (hs)/beep i/o c t hs x ei1 x x port f1 beep signal output 27 17 - pf2 (hs) i/o c t hs x ei1 x x port f2 28 - - pf3/ocmp2_a/ain9 i/o c t x xxxxport f3 timer a out- put compare 2 adc ana- log input 9 29 18 5 pf4/ocmp1_a/ ain10 i/o c t x xxxxport f4 timer a out- put compare 1 adc ana- log input 10 30 - - pf5/icap2_a/ain11 i/o c t x xxxxport f5 timer a input capture 2 adc ana- log input 11 31 19 6 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 32 20 7 pf7 (hs)/extclk_a i/o c t hs x xxxport f7 timer a external clock source 33 21 - v dd_0 s digital main supply voltage 34 22 - v ss_0 s digital ground voltage 35 23 8 pc0/ocmp2_b/ ain12 i/o c t x xxxxport c0 timer b out- put compare 2 adc ana- log input 12 36 24 9 pc1/ocmp1_b/ ain13 i/o c t x xxxxport c1 timer b out- put compare 1 adc ana- log input 13 37 25 10 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 38 26 11 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 39 27 12 pc4/miso/iccdata i/o c t x xxxport c4 spi master in / slave out data icc data input 40 28 13 pc5/mosi/ain14 i/o c t x xxxxport c5 spi master out / slave in data adc ana- log input 14 41 29 29 pc6/sck/iccclk i/o c t x xxxport c6 spi serial clock icc clock output caution: negative cur- rent injection not al- lowed on this pin 42 30 15 pc7/ss /ain15 i/o c t x xxxxport c7 spi slave se- lect (active low) adc ana- log input 15 43 - - pa0 i/o c t x ei0 x x port a0 44 - - pa1 i/o c t x ei0 x x port a1 pin n pin name type level port main function (after reset) alternate function lqfp64 lqfp44 lqfp32 input output input output float wpu int ana od pp st72321rx st72321arx st72321jx 12/193 notes : 1. in the interrupt input column, ?eix? defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. in the open drain output column, ?t? defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see see ?i/o ports? on page 46. and section 12.8 i/o port pin character- 45 - - pa2 i/o c t x ei0 x x port a2 46 31 16 pa3 (hs) i/o c t hs x ei0 x x port a3 47 32 - v dd_1 s digital main supply voltage 48 33 - v ss_1 s digital ground voltage 49 34 17 pa4 (hs) i/o c t hs x xxxport a4 50 35 - pa5 (hs) i/o c t hs x xxxport a5 51 36 18 pa6 (hs)/sdai i/o c t hs x tport a6 i 2 c data 1) 52 37 19 pa7 (hs)/scli i/o c t hs x tport a7 i 2 c clock 1) 53 38 20 v pp / iccsel i must be tied low. in flash program- ming mode, this pin acts as the pro- gramming voltage input v pp . see section 12.9.2 for more details. high voltage must not be applied to rom devices 54 39 21 reset i/o c t top priority non maskable interrupt. 55 - - evd external voltage detector 56 - - tli i c t x top level interrupt input pin 57 40 22 v ss_2 s digital ground voltage 58 41 23 osc2 3) i/o resonator oscillat or inverter output 59 42 24 osc1 3) i external clock input or resonator os- cillator inverter input 60 43 25 v dd_2 s digital main supply voltage 61 44 26 pe0/tdo i/o c t x x x x port e0 sci transmit data out 62 1 27 pe1/rdi i/o c t x x x x port e1 sci receive data in 63 - - pe2 (flash device) i/o c t x port e2 caution: in flash devices this port is always input with weak pull-up. pe2 (rom device) x xx port e2 caution: in rom devices, no weak pull-up present on this port. in lqfp44 this pin is not connected to an internal pull-up like other unbond- ed pins (see note 4). it is recommend- ed to configure it as output push pull to avoid added current consumption. 64 - - pe3 i/o c t x xxxport e3 pin n pin name type level port main function (after reset) alternate function lqfp64 lqfp44 lqfp32 input output input output float wpu int ana od pp st72321rx st72321arx st72321jx 13/193 istics for more details. 3. osc1 and osc2 pins connect a crystal/ceramic reso nator, or an external source to the on-chip oscil- lator; see section 1 description and section 12.5 clock and timing characteristics for more details. 4. on the chip, each i/o port may have up to 8 pads: ? ads that are not bonded to external pins are forced by hardware in input pull-up configuration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. 5. pull-up always activated on pe2 see limitation section 15.4.6 . 6. it is mandatory to connect all available v dd and v ref pins to the supply voltage and all v ss and v ssa pins to ground. st72321rx st72321arx st72321jx 14/193 3 register & memory map as shown in figure 4 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 2kbytes of ram and up to 60kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. important: memory locations marked as ?re- served? must never be accessed. accessing a re- seved area can have unpredictable effects on the device. related documentation an 985: executing code in st7 ram figure 4. memory map 0000h ram program memory (60k, 48k or 32k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see table 3 ) 1000h ffdfh ffe0h ffffh (see table 8 ) 0880h reserved 087fh short addressing ram (zero page) 256 bytes stack 16-bit addressing ram 0100h 01ffh 0080h 0200h 00ffh or 087fh 32 kbytes 8000h 60 kbytes 48 kbytes ffffh 1000h 4000h (2048, 1536 or 1024 bytes) or 067fh or 047fh st72321rx st72321arx st72321jx 15/193 table 3. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a 2) padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 0003h 0004h 0005h port b 2) pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 1) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d 2) pddr pdddr pdor port d data register port d data direction register port d option register 00h 1) 00h 00h r/w r/w r/w 000ch 000dh 000eh port e 2) pedr peddr peor port e data register port e data direction register port e option register 00h 1) 00h 00h r/w r/w 2) r/w 2) 000fh 0010h 0011h port f 2) pfdr pfddr pfor port f data register port f data direction register port f option register 00h 1) 00h 00h r/w r/w r/w 0012h to 0017h reserved area (6 bytes) 0018h 0019h 001ah 001bh 001ch 001dh 001eh i 2 c i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c own address register 1 i 2 c own address register2 i 2 c data register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w 001fh 0020h reserved area (2 bytes) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h itc ispr0 ispr1 ispr2 ispr3 interrupt software pr iority register 0 interrupt software pr iority register 1 interrupt software pr iority register 2 interrupt software pr iority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h eicr external interrupt control register 00h r/w 0029h flash fcsr flash contro l/status register 00h r/w st72321rx st72321arx st72321jx 16/193 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh sicsr system integrity contro l/status register 000x 000x b r/w 002ch 002dh mcc mccsr mccbcr main clock control / status register main clock controller: beep control register 00h 00h r/w r/w 002eh to 0030h reserved area (3 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tacsr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate c ounter high register timer a alternate c ounter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxxx x0xx b xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved area (1 byte) 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbcsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate c ounter high register timer b alternate c ounter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxxx x0xx b xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00h x000 0000b 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w address block register label register name reset status remarks st72321rx st72321arx st72321jx 17/193 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 0058h to 006fh reserved area (24 bytes) 0070h 0071h 0072h adc adccsr adcdrh adcdrl control/status register data high register data low register 00h 00h 00h r/w read only read only 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh pwm art pwmdcr3 pwmdcr2 pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr articcsr articr1 articr2 pwm ar timer duty cycle register 3 pwm ar timer duty cycle register 2 pwm ar timer duty cycle register 1 pwm ar timer duty cycle register 0 pwm ar timer control register auto-reload timer cont rol/status register auto-reload timer counter access register auto-reload timer auto-reload register ar timer input captur e control/status reg. ar timer input capture register 1 ar timer input capture register 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only 007eh 007fh reserved area (2 bytes) address block register label register name reset status remarks st72321rx st72321arx st72321jx 18/193 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a byte-by-byte ba- sis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features three flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be pro- grammed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be pro- grammed or erased without removing the de- vice from the application board. ? iap (in-application programming) in this mode, all sectors except sector 0, can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram read-out protection register access securi ty system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see table 4 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 5 ). they are mapped in the upper part of the st7 addressing space so the reset and in- terrupt vectors are located in sector 0 (f000h- ffffh). table 4. sectors available in flash devices 4.3.1 read-out protection read-out protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. even if no protection can be considered as to- tally unbreakable, the feature provides a very high level of protection for a general purpose microcon- troller. in flash devices, this prot ection is removed by re- programming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by mask option specified in the option list. note: in flash devices, the lvd is not supported if read-out protection is enabled. figure 5. memory map and sector address flash size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k st72321rx st72321arx st72321jx 19/193 flash program memory (cont?d) 4.4 icc interface icc needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see figure 6 ). these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input/output serial data pin ? iccsel/v pp : programming voltage ? osc1(or oscin): main clock input for exter- nal source (optional) ?v dd : application board power supply (option- al, see figure 6 , note 3) figure 6. typical icc interface notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icc session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. when using a classical rc network with r>1k or a reset man- agement ic with open drain output and pull-up re- sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 or os- cin pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator ca pability need to have osc2 grounded in this case. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4) st72321rx st72321arx st72321jx 20/193 flash program memory (cont?d) 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circu it communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the spe- cific microcontroller device, the user needs only to implement the icp hardware interface on the ap- plication board (see figure 6 ). for more details on the pin locations, refer to the device pinout de- scription. 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci, usb or can interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase pro- tected to allow recovery in case errors occur dur- ing the programming operation. 4.7 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.7.1 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. figure 7. flash control/status register address and reset value 70 00000000 address (hex.) register label 76543210 0029h fcsr reset value00000000 st72321rx st72321arx st72321jx 21/193 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 5.3 cpu registers the six cpu registers shown in figure 1 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 8. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value st72321rx st72321arx st72321jx 22/193 central processing unit (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it?s a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 st72321rx st72321arx st72321jx 23/193 central processing unit (cont?d) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 2 ). since the stack is 256 bytes deep, the 8 most sig- nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 2 . ? when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five location s in the stack area. figure 9. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h st72321rx st72321arx st72321jx 24/193 6 supply, reset an d clock management the device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 11 . for more details, refer to dedicated parametric section. main features optional pll for multiplying the frequency by 2 (not to be used with internal rc oscillator) reset sequence manager (rsm) multi-oscillator cloc k management (mo) ? 5 crystal/ceramic resonator oscillators ? 1 internal rc oscillator system integrity management (si) ? main supply low voltage detection (lvd) ? auxiliary voltage detect or (avd) with interrupt capability for monitori ng the main supply or the evd pin 6.1 phase locked loop if the clock frequency input to the pll is in the range 2 to 4 mhz, the pll can be used to multiply the frequency by two to obtain an f osc2 of 4 to 8 mhz. the pll is enabled by option byte. if the pll is disabled, then f osc2 = f osc /2. caution: the pll is not recommended for appli- cations where timing accuracy is required. see ?pll characteristics? on page 151. figure 10. pll block diagram figure 11. clock, reset and supply block diagram 0 1 pll option bit pll x 2 f osc2 / 2 f osc low voltage detector (lvd) f osc2 auxiliary voltage detector (avd) multi- oscillator (mo) osc1 reset v ss evd v dd reset sequence manager (rsm) osc2 main clock avd interrupt request controller pll system integrity management watchdog sicsr timer (wdg) with realtime clock (mcc/rtc) avd avd avd lvd rf ie wdg rf 0 1 f osc (option) 0 s f f cpu 00 st72321rx st72321arx st72321jx 25/193 6.2 multi-osc illator (mo) the main clock of the st7 can be generated by three different source types coming from the multi- oscillator block: an external source 4 crystal or ceramic resonator oscillators an internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 5 . refer to the electrical characteristics section for more details. caution: the osc1 and/or osc2 pins must not be left unconnected. for the purposes of failure mode and effect analysis, it should be noted that if the osc1 and/or osc2 pins are left unconnected, the st7 main oscillator may start and, in this con- figuration, could generate an f osc clock frequency in excess of the allowed maximum (>16mhz.), putting the st7 in an unsafe/undefined state. the product behaviour must therefore be considered undefined when the osc pins are left unconnect- ed. external clock source in this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. crystal/ceramic oscillators this family of oscillators has the advan tage of pro- ducing a very accurate rate on the main clock of the st7. the selection with in a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 14.1 on page 175 for more details on the frequency ranges). in this mode of the multi-oscil- lator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization ti me. the loading capaci- tance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. internal rc oscillator this oscillator allows a lo w cost solution for the main clock of the st7 using only an internal resis- tor and capaci tor. internal rc oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require ac- curate timing. in this mode, the two oscilla tor pins have to be tied to ground. table 5. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7 st72321rx st72321arx st72321jx 26/193 6.3 reset sequence manager (rsm) 6.3.1 introduction the reset sequence manager includes three re- set sources as shown in figure 13 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 12 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (selected by option byte) reset vector fetch the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilise an d ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application (see section 14.1 on page 175 ). the reset vector fetch phase duration is 2 clock cycles. figure 12. reset sequence phases caution: when the st7 is unprogrammed or fully erased, the flash is bl ank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. 6.3.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see ?control pin characteristics? on page 159 for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 14 ). this de- tection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 13. reset block diagram reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter st72321rx st72321arx st72321jx 27/193 reset sequence manager (cont?d) the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. if the external reset pulse is shorter than t w(rstl)out (see short ext. reset in figure 14 ), the signal on the reset pin may be stretched. other- wise the delay will not be applied (see long ext. reset in figure 14 ). starting from the external re- set pulse recognition, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 6.3.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. (see ?operating conditions? on page 140 ) a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. 6.3.4 internal low voltage detector (lvd) reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd st72321rx st72321arx st72321jx 29/193 system integrity management (cont?d) 6.4.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main sup- ply or the external evd pin voltage level (v evd ). the v it- reference value for fa lling voltage is lower than the v it+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly read- able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution : the avd function is active only if the lvd is enabled through the option byte. 6.4.2.1 monitoring the v dd main supply this mode is selected by clearing the avds bit in the sicsr register. the avd voltage threshold va lue is relative to the selected lvd threshold configured by option byte (see section 14.1 on page 175 ). if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit toggles). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon- troller. see figure 16 . the interrupt on the rising edge is used to inform the application that the v dd warning state is over. if the voltage rise time t rv is less than 256 or 4096 cpu cycles (depending on the reset delay select- ed by option byte), no avd interrupt will be gener- ated when v it+(avd) is reached. if t rv is greater than 256 or 4096 cycles then: ? if the avd interrupt is enabled before the v it+(avd) threshold is reached, then 2 avd inter- rupts will be received: the first when the avdie bit is set, and the second when the threshold is reached. ? if the avd interrupt is enabled after the v it+(avd) threshold is reached then only one avd interrupt will occur. figure 16. using the avd to monitor v dd (avds bit=0) v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 1 t rv voltage rise time st72321rx st72321arx st72321jx 30/193 system integrity management (cont?d) 6.4.2.2 monitoring a voltage on the evd pin this mode is selected by setting the avds bit in the sicsr register. the avd circuitry can generate an interrupt when the avdie bit of the sicsr register is set. this in- terrupt is generated on the rising and falling edges of the comparator output. this means it is generat- ed when either one of these two events occur: ?v evd rises up to v it+(evd) ?v evd falls down to v it-(evd) the evd function is illustrated in figure 17 . for more details, refer to the electrical character- istics section. figure 17. using the voltage detector to monitor the evd pin (avds bit=1) 6.4.3 low power modes 6.4.3.1 interrupts the avd interrupt event generate an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is re- set (rim instruction). v evd v it+(evd) v it-(evd) avdf 0 0 1 if avdie = 1 v hyst avd interrupt request interrupt process interrupt process mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no st72321rx st72321arx st72321jx 31/193 system integrity management (cont?d) 6.4.4 register description system integrity (si) control/status register (sicsr) read/write reset value: 000x 000x (00h) bit 7 = avds voltage detection selection this bit is set and cleared by software. voltage de- tection is available only if the lvd is enabled by option byte. 0: voltage detection on v dd supply 1: voltage detection on evd pin bit 6 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt informa- tion is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled bit 5 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen- erated when the avdf bit changes value. refer to figure 16 and to section 6.4.2.1 for additional de- tails. 0: v dd or v evd over v it+(avd) threshold 1: v dd or v evd under v it-(avd) threshold bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bits 31 = reserved, must be kept cleared. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was generat- ed by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. caution: when the lvd is not activated with the associated option byte, the wdgrf flag can not be used in the application. 70 avd s avd ie avd f lvd rf 000 wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x st72321rx st72321arx st72321jx 32/193 7 interrupts 7.1 introduction the st7 enhanced interrupt management pro- vides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrup t priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non maskable events: reset, trap ? 1 maskable top level event: tli this interrupt management is based on: ? bit 5 and bit 3 of the cpu cc register (i1:0), ? interrupt software priority registers (isprx), ? fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with th e standard (not nest- ed) st7 interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt so ftware priority level of each interrupt vector (see table 6 ). the process- ing flow is shown in figure 18 when an interrupt request has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ?interrupt mapping? table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the pr evious level will resume. table 6. interrupt software priority levels figure 18. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset trap pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt st72321rx st72321arx st72321jx 33/193 interrupts (cont?d) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: ? the highest software priority interrupt is serviced, ? if several interr upts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 19 describes this decision process. figure 19. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : tli, reset and trap can be considered as having the highest software priority in the deci- sion process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (external or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 18 ). after stacking the pc, x, a and cc registers (except for r eset), the co rresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart in figure 18 . caution: trap can be interrupted by a tli. reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. tli (top level hardware interrupt) this hardware in terrupt occurs when a specific edge is detected on the dedicated tli pin. it will be serviced according to the flowchart in figure 18 as a trap. caution : a trap instruction must not be used in a tli service routine. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitiv- ity is software selectable through the external in- terrupt control register (eicr). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the ?interrupt mapping? table. a peripheral inter- rupt occurs when a specific flag is set in the pe- ripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will theref ore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced st72321rx st72321arx st72321jx 34/193 interrupts (cont?d) 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ?exit from halt? in ?interrupt mapping? table). when several pending interrupts are present while exit- ing halt mode, the first one serviced can only be an interrupt with ex it from halt mode capability and it is selected through the same decision proc- ess shown in figure 19 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent & nested management the following figure 20 and figure 21 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 21 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 20. concurrent interrupt management figure 21. nested interrupt management main it4 it2 it1 trap it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 trap it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 trap main it0 it2 it1 it4 trap it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes st72321rx st72321arx st72321jx 35/193 interrupts (cont?d) 7.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see ?interrupt dedicated instruction set? table). *note : tli, trap and reset events can interrupt a level 3 program. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. ? each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. ? each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. ? level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the tli, reset, and trap vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the tli can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits st72321rx st72321arx st72321jx 36/193 interrupts (cont?d) table 7. dedicated interrupt instruction set note : during the execution of an interrupt routine, the halt, popcc, rim, si m and wfi instructions change the current software priority up to the next iret instructi on or one of the previously mentioned instructions. instruction new descripti on function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 (level 3) i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 st72321rx st72321arx st72321jx 37/193 interrupts (cont?d) table 8. interrupt mapping notes: 1. exit from halt possible when spi is in slave mode. 2. exit from halt possible when pwm art is in external clock mode. 3. only a reset or mcc/rtc interrupt can be used to wake -up from active halt mode. 7.6 external interrupts 7.6.1 i/o port interrupt sensitivity the external interrupt se nsitivity is controlled by the ipa, ipb and isxx bits of the eicr register ( figure 22 ). this control allows to have up to 4 fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: falling edge rising edge falling and rising edge falling edge and low level rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). this means that interrupts must be disabled before changing sensitivity. the pending interrupts are cleared by writing a dif- ferent value in the isx[1:0], ipa or ipb bits of the eicr. n source block description register label priority order exit from halt 3) address vector reset reset n/a yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 tli external top level interrupt eicr yes fffah-fffbh 1 mcc/rtc main clock controller time base interrupt mccsr higher priority yes fff8h-fff9h 2 ei0 external interrupt port a3..0 n/a yes fff6h-fff7h 3 ei1 external interrupt port f2..0 yes fff4h-fff5h 4 ei2 external interrupt port b3..0 yes fff2h-fff3h 5 ei3 external interrupt port b7..4 yes fff0h-fff1h 6 not used ffeeh-ffefh 7 spi spi peripheral interrupts spicsr yes 1 ffech-ffedh 8 timer a timer a peripheral interrupts tasr no ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr no ffe8h-ffe9h 10 sci sci peripheral interrupts scisr lower priority no ffe6h-ffe7h 11 avd auxiliary voltage detector interrupt sicsr no ffe4h-ffe5h 12 i2c i2c peripheral interrupts (see periph) no ffe2h-ffe3h 13 pwm art pwm art interrupt artcsr yes 2 ffe0h-ffe1h st72321rx st72321arx st72321jx 38/193 interrupts (cont?d) figure 22. external interrupt control bits is10 is11 eicr sensitivity control pbor.3 pbddr.3 ipb bit pb3 ei2 interrupt source port b [3:0] interrupts pb3 pb2 pb1 pb0 is10 is11 eicr sensitivity control pbor.7 pbddr.7 pb7 ei3 interrupt source port b [7:4] interrupts pb7 pb6 pb5 pb4 is20 is21 eicr sensitivity control paor.3 paddr.3 ipa bit pa3 ei0 interrupt source port a [3:0] interrupts pa3 pa2 pa1 pa0 is20 is21 eicr sensitivity control pfor.2 pfddr.2 pf2 ei1 interrupt source port f [2:0] interrupts pf2 pf1 pf0 st72321rx st72321arx st72321jx 39/193 7.7 external interrupt control register (eicr) read/write reset value: 0000 0000 (00h) bit 7:6 = is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: - ei2 (port b3..0) - ei3 (port b7..4) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 5 = ipb interrupt polarity for port b this bit is used to invert the sensitivity of the port b [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion bit 4:3 = is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: - ei0 (port a3..0) - ei1 (port f2..0) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 2 = ipa interrupt polarity for port a this bit is used to invert the sensitivity of the port a [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion bit 1 = tlis tli sensitivity this bit allows to toggle th e tli edge sensitivity. it can be set and cleared by software only when tlie bit is cleared. 0: falling edge 1: rising edge bit 0 = tlie tli enable this bit allows to enable or disable the tli capabil- ity on the dedicated pin. it is set and cleared by software. 0: tli disabled 1: tli enabled note : a parasitic interrupt can be generated when clearing the tlie bit. 70 is11 is10 ipb is21 is20 ipa tlis tlie is11 is10 external interrupt sensitivity ipb bit =0 ipb bit =1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is11 is10 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity ipa bit =0 ipa bit =1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge st72321rx st72321arx st72321jx 40/193 interrupts (cont?d) table 9. nested interrupts register map and reset values address (hex.) register label 76543210 0024h ispr0 reset value ei1 ei0 mcc tli i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0025h ispr1 reset value spi ei3 ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 reset value avd sci timer b timer a i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value1111 pwmart i2c i1_13 1 i0_13 1 i1_12 1 i0_12 1 0028h eicr reset value is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 0 tlis 0 tlie 0 st72321rx st72321arx st72321jx 41/193 8 power saving modes 8.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 23 ): slow, wait (slow wait), ac- tive halt and halt. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency di vided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by callin g the specific st7 software instruction whose action depends on the oscillator status. figure 23. power saving mode transitions 8.2 slow mode this mode has two targets: ? to reduce power consumption by decreasing the internal clock in the device, ? to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and pe- ripherals are clocked at this lower frequency (f cpu ). note : slow-wait mode is activated when enter- ing the wait mode while the device is already in slow mode. figure 24. slow mode clock transitions power consumption wait slow run active halt high low slow wait halt 00 01 sms cp1:0 f cpu new slow normal run mode mccsr frequency request request f osc2 f osc2 /2 f osc2 /4 f osc2 st72321rx st72321arx st72321jx 42/193 power saving modes (cont?d) 8.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to ?10?, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wa it mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 25 . figure 25. wait mode flow-chart note: 1. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx 1) on 256 or 4096 cpu clock cycle delay st72321rx st72321arx st72321jx 43/193 power saving modes (cont?d) 8.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the ?halt? instruc- tion. the decision to enter either in active-halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in mccsr register). 8.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the ?halt? in- struction when the oie bit of the main clock con- troller status register (mccsr) is set (see section 10.2 on page 57 for more details on the mccsr register). the mcu can exit active-halt mode on recep- tion of an mcc/rtc interrupt or a reset. when exiting active-halt mode by means of an inter- rupt, no 256 or 4096 cpu cycle delay occurs. the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 27 ). when entering active-halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable in- terrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, on ly the main oscillator and its associated counter (mcc/rtc) are run- ning to keep a wake-up time base. all other periph- erals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). the safeguard against staying locked in active- halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capability of one of the oscillators is selected (mccsr.oie bit set), entering active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. caution: when exiting active-halt mode fol- lowing an mcc/rtc interrupt, oie bit of mccsr register must not be cleared before t delay after the interrupt occurs (t delay = 256 or 4096 t cpu de- lay depending on option byte). otherwise, the st7 enters halt mode for the remaining t delay peri- od. figure 26. active-halt timing overview figure 27. active-halt mode flow-chart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripheral clocked with an external clock source can still be active. 3. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and restored when the cc register is popped. 4. only the mcc/rtc interrupt can exit the mcu from active-halt mode. mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode halt run run 256 or 4096 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [mccsr.oie=1] halt instruction reset y n n y cpu oscillator peripherals 2) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 3) on cpu oscillator peripherals i[1:0] bits on on xx 3) on 256or4096cpuclock cycle delay (mccsr.oie=1) interrupt 4) st72321rx st72321arx st72321jx 44/193 power saving modes (cont?d) 8.4.2 halt mode the halt mode is the lo west power consumption mode of the mcu. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 10.2 on page 57 for more de- tails on the mccsr register). the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 8, ?interrupt mapping,? on page 37) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immedi ately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. afte r the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see fig- ure 29 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ?10b?to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see sec- tion 14.1 on page 175 for more details). figure 28. halt timing overview figure 29. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 8, ?interrupt mapping,? on page 37 for more details. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie=0] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 (mccsr.oie=0) cycle st72321rx st72321arx st72321jx 45/193 power saving modes (cont?d) 8.4.2.1 halt mode recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? when using an external interrupt to wake up the microcontroller, reinitia lize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. ? for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. ? as the halt instruction clears the interrupt mask in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits be- fore executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corre- sponding to the wake-up event (reset or external interrupt). related documentation an 980: st7 keypad decoding techniques, im- plementing wake-up on keystroke an1014: how to minimize the st7 power con- sumption an1605: using an active rc to wakeup the st7lite0 from power saving mode st72321rx st72321arx st72321jx 46/193 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: ? transfer of data through digital inputs and outputs and for specific pins: ? external interrupt generation ? alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 functional description each port has two main registers: ? data register (dr) ? data direction register (ddr) and one optional register: ? option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 1 9.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. 3. do not use read/modify /write instructions (bset or bres) to modify the dr register as this might corrupt the dr content for i/os configured as input. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sens itivity is independently programmable using the sensitivity bits in the eicr register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the applicati on) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 9.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 9.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pull open-drain 0v ss vss 1v dd floating st72321rx st72321arx st72321jx 47/193 i/o ports (cont?d) figure 30. i/o port general block diagram table 10. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) external source (ei x ) interrupt cmos schmitt trigger register access st72321rx st72321arx st72321jx 48/193 i/o ports (cont?d) table 11. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and th e associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) condition pad v dd r pu external interrupt data b u s pull-up interrupt dr register access w r source (ei x ) dr register condition alternate input not implemented in true open drain i/o ports analog input pad r pu data b u s dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data b u s dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports st72321rx st72321arx st72321jx 49/193 i/o ports (cont?d) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 9.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 2 on page 4. other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 31. interrupt i/o port state transitions 9.4 low power modes 9.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or st72321rx st72321arx st72321jx 50/193 i/o ports (cont?d) 9.5.1 i/o port implementation the i/o port register configurations are summa- rised as follows. standard ports pa5:4, pc7:0, pd7:0, pe7:3, pe1:0, pf7:3, interrupt ports pa2:0, pb6:5, pb4, pb2:0, pf1:0 (with pull-up) pa3, pb7, pb3, pf2 (without pull-up) true open drain ports pa7:6 pull-up input port pe2 table 12. port configuration mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr floating input 0 open drain (high sink ports) 1 mode pull-up input port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:6 floating true open-drain pa5:4 floating pull-up open drain push-pull pa3 floating floating interrupt open drain push-pull pa2:0 floating pull-up interrupt open drain push-pull port b pb7, pb3 floating floating interrupt open drain push-pull pb6:5, pb4, pb2:0 floating pull-up interrupt open drain push-pull port c pc7:0 floating pull-up open drain push-pull port d pd7:0 floating pull-up open drain push-pull port e pe7:3, pe1:0 floating pull-up open drain push-pull pe2 (flash de- vices) pull-up input only pe2 (rom de- vices) floating floating open drain push-pull port f pf7:3 floating pull-up open drain push-pull pf2 floating floating interrupt open drain push-pull pf1:0 floating pull-up interrupt open drain push-pull st72321rx st72321arx st72321jx 51/193 i/o ports (cont?d) table 13. i/o port register map and reset values related documentation an 970: spi communication between st7 and eeprom an1045: s/w implementation of i2c bus master an1048: software lcd driver address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor st72321rx st72321arx st72321jx 52/193 10 on-chip peripherals 10.1 watchdog timer (wdg) 10.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter?s contents before the t6 bit be- comes cleared. 10.1.2 main features programmable free-running downcounter programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 10.1.3 functional description the counter value stored in the watchdog control register (wdgcr bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling the reset pin low for typically 30s. the application program must write in the wdgcr register at regular intervals during normal operation to prevent an mcu reset. this down- counter is free-running: it counts down even if the watchdog is disabled. the value to be stored in the wdgcr register must be between ffh and c0h: ? the wdga bit is set (watchdog enabled) ? the t6 bit is set to prevent generating an imme- diate reset ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 2. ap- proximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writ- ing to the wdgcr register (see figure 3 ). following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. figure 32. watchdog block diagram reset wdga 6-bit downcounter (cnt) f osc2 t6 t0 wdg prescaler watchdog control register (wdgcr) div 4 t1 t2 t3 t4 t5 12-bit mcc rtc counter msb lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register) st72321rx st72321arx st72321jx 53/193 watchdog timer (cont?d) 10.1.4 how to program the watchdog timeout figure 2 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (cnt) and the resulting timeout duration in milli- seconds. this can be used for a quick calculation without taking the timing variations into account. if more precision is needed, use the formulae in fig- ure 3 . caution: when writing to the wdgcr register, al- ways write 1 in the t6 bit to avoid generating an immediate reset. figure 33. approximate timeout duration cnt value (hex.) watchdog timeout (ms) @ 8 mhz. f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 st72321rx st72321arx st72321jx 54/193 watchdog timer (cont?d) figure 34. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example: with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 cnt t osc2 + = t max t max0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = st72321rx st72321arx st72321jx 55/193 watchdog timer (cont?d) 10.1.5 low power modes 10.1.6 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description. 10.1.7 using halt mode with the wdg (wdghalt option) the following recommenda tion applies if halt mode is used when the watchdog is enabled. ? before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. 10.1.8 interrupts none. 10.1.9 register description control register (wdgcr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit counter (msb to lsb). these bits contain the value of the watchdog counter. it is decremented every 16384 f osc2 cy- cles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). mode description slow no effect on watchdog. wait no effect on watchdog. halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watch- dog counter is decremented once and t hen stops counting and is no longer able to generate a watchdog reset until the mcu receives an external inter- rupt or a reset. if an external interrupt is received, the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is gener ated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for applica- tion recommendations see section 0.1.7 below. 0 1 a reset is generated. 1x no reset is generated. the mcu ente rs active halt mode. the watchdog counter is not decremented. it stop counting. when the mcu receives an oscillator interrupt or external inte rrupt, the watchdog restarts counting im- mediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks. 70 wdga t6 t5 t4 t3 t2 t1 t0 st72321rx st72321arx st72321jx 56/193 table 14. watchdog timer register map and reset values address (hex.) register label 76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 st72321rx st72321arx st72321jx 57/193 10.2 main clock controller with re al time clock and beeper (mcc/rtc) the main clock controller co nsists of three differ- ent functions: a programmable cpu clock prescaler a clock-out signal to supply external devices a real time clock timer with interrupt capability each function can be used independently and si- multaneously. 10.2.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal periph- erals. it manages slow power saving mode (see section 8.2 slow mode for more details). the prescaler selects the f cpu main clock frequen- cy and is controlled by three bits in the mccsr register: cp[1:0] and sms. 10.2.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f cpu clock to drive external devices. it is controlled by the mco bit in the mccsr register. caution : when selected, the clock out pin sus- pends the clock during active-halt mode. 10.2.3 real time clock timer (rtc) the counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. four different time bases depend- ing directly on f osc2 are available. the whole functionality is controlled by four bits of the mcc- sr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 8.4 ac- tive-halt and halt modes for more details. 10.2.4 beeper the beep function is controlled by the mccbcr register. it can output three selectable frequencies on the beep pin (i/o port alternate function). figure 35. main clock controller (mcc/rtc) block diagram div 2, 4, 8, 16 mcc/rtc interrupt sms cp1 cp0 tb1 tb0 oie oif cpu clock mccsr 12-bit mcc rtc counter to cpu and peripherals f osc2 f cpu mco mco bc1 bc0 mccbcr beep selection beep signal 1 0 to watchdog timer div 64 st72321rx st72321arx st72321jx 58/193 main clock controller with real time clock (cont?d) 10.2.5 low power modes 10.2.6 interrupts the mcc/rtc interrupt event generates an inter- rupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). note : the mcc/rtc interrupt wakes up the mcu from active-halt mode, not from halt mode. 10.2.7 register description mcc control/status register (mccsr) read/write reset value: 0000 0000 (00h ) bit 7 = mco main clock out selection this bit enables the mco al ternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) note : to reduce power consumption, the mco function is not active in active-halt mode. bit 6:5 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 4 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc2 1: slow mode. f cpu is given by cp1, cp0 see section 8.2 slow mode and section 10.2 main clock controller with real time clock and beeper (mcc/rtc) for more de- tails. bit 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active- halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the device to exit from wait mode. active- halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with ?exit from halt? capability. interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no 1) 70 mco cp1 cp0 sms tb1 tb0 oie oif f cpu in slow mode cp1 cp0 f osc2 / 2 0 0 f osc2 / 4 0 1 f osc2 / 8 1 0 f osc2 / 16 1 1 counter prescaler time base tb1 tb0 f osc2 =4mhz f osc2 =8mhz 16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 1 st72321rx st72321arx st72321jx 59/193 main clock controller with real time clock (cont?d) bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the mccsr register. it indicates when set that the main oscillator has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and b set instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. mcc beep control register (mccbcr) read/write reset value: 0000 0000 (00h) bit 7:2 = reserved, must be kept cleared. bit 1:0 = bc[1:0] beep control these 2 bits select the pf1 pin beep capability. the beep output signal is available in active- halt mode but has to be disabled to reduce the consumption. table 15. main clock controller register map and reset values 70 000000bc1bc0 bc1 bc0 beep mode with f osc2 =8mhz 00 off 01 ~2-khz output beep signal ~50% duty cycle 10 ~1-khz 1 1 ~500-hz address (hex.) register label 76543210 002bh sicsr reset value avds 0 avdie 0 avdf 0 lvdrf x000 wdgrf x 002ch mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 002dh mccbcr reset value000000 bc1 0 bc0 0 st72321rx st72321arx st72321jx 60/193 10.3 pwm auto-reload timer (art) 10.3.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto reload counter with com pare/capture capabilities and of a 7-bit prescaler clock source. these resources allow five possible operating modes: ? generation of up to 4 independent pwm signals ? output compare and time base interrupt ? up to two input capture functions ? external event detector ? up to two external interrupt sources the three first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 36. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port function alternate ocrx compare register programmable prescaler 8-bit counter (car register) arr register icrx register load opx polarity control oex pwmcr mux f cpu dcrx register load f counter artclk f ext articx icfx icsx iccsr load icx interrupt iciex input capture control st72321rx st72321arx st72321jx 61/193 on-chip peripherals (cont?d) 10.3.2 functional description counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (artcar). when a counter overflow occurs, the counter is automatically reloaded with the contents of the artarr register (the prescaler is not affected). counter clock and prescaler the counter clock fr equency is given by: f counter = f input / 2 cc[2:0] the timer counter?s input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (artcsr). thus the division factor of the prescal- er can be set to 2 n (where n = 0, 1,..7). this f input frequency source is selected through the excl bit of the artcsr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the artcsr register. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. counter and prescaler initialization after reset, the counter and the prescaler are cleared and f input = f cpu . the counter can be initialized by: ? writing to the artarr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the artcsr reg- ister. ? writing to the artcar counter access register, in both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. direct access to the pre scaler is not possible. output compare control the timer compare function is based on four differ- ent comparisons with the counter (one for each pwmx output). each comparison is made be- tween the counter value and an output compare register (ocrx) value. this ocrx register can not be accessed directly, it is loaded from the duty cy- cle register (pwmdcrx) at each overflow of the counter. this double buffering method avoids glitch gener- ation when changing the duty cycle on the fly. figure 37. output compare control counter fdh feh ffh fdh feh ffh fdh feh artarr=fdh f counter ocrx pwmdcrx fdh feh fdh feh ffh pwmx st72321rx st72321arx st72321jx 62/193 on-chip peripherals (cont?d) independent pwm signal generation this mode allows up to four pulse width modulat- ed signals to be generated on the pwmx output pins with minimum core processing overhead. this function is stopped during halt mode. each pwmx output signal can be selected inde- pendently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as out- put push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the artarr register value. f pwm = f counter / (256 - artarr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be no ted that the rel oad values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the artarr reg- ister. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - artarr) note : to get the maximum resolution (1/256), the artarr register must be 0. with this maximum resolution, 0% and 100% can be obtained by changing the polarity. figure 38. pwm auto-reload timer function figure 39. pwm signal from 0% to 100% duty cycle duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (artarr) (pwmdcrx) with oex=1 and opx=1 counter counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh artarr=fdh f counter st72321rx st72321arx st72321jx 63/193 on-chip peripherals (cont?d) output compare and time base interrupt on overflow, the ovf flag of the artcsr register is set and an overflow interrupt request is generat- ed if the overflow interrupt enable bit, oie, in the artcsr register, is set. the ovf flag must be re- set by the user software. this interrupt can be used as a time base in the application. external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the artarr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - artarr caution: the external clock function is not availa- ble in halt mode. if halt mode is used in the ap- plication, prior to execut ing the halt instruction, the counter must be disabled by clearing the tce bit in the artcsr register to avoid spurious coun- ter increments. figure 40. external event detector example (3 counts) counter t fdh feh ffh fdh ovf artcsr read interrupt artarr=fdh f ext =f counter feh ffh fdh if oie=1 interrupt if oie=1 artcsr read st72321rx st72321arx st72321jx 64/193 on-chip peripherals (cont?d) input capture function this mode allows the measurement of external signal pulse widths through articrx registers. each input capture can generate an interrupt inde- pendently on a selected input signal transition. this event is flagged by a set of the corresponding cfx bits of the input capture control/status regis- ter (articcsr). these input capture interrupts are enabled through the ciex bits of the articcsr register. the active transition (falling or rising edge) is soft- ware programmable through the csx bits of the articcsr register. the read only input capture registers (articrx) are used to latch the auto-reload counter value when a transition is detected on the articx pin (cfx bit set in articcsr register). after fetching the interrupt vector, the cfx flags can be read to identify the interrupt source. note : after a capture detection, data transfer in the articrx register is in hibited until it is read (clearing the cfx bit). the timer interrupt remain s pending while the cfx flag is set when the interr upt is enabled (ciex bit set). this means, the articrx register has to be read at each capture event to clear the cfx flag. the timing resolution is given by auto-reload coun- ter cycle time (1/f counter ). note: during halt mode, if both input capture and external clock are enabled, the articrx reg- ister value is not guaranteed if the input capture pin and the external cloc k change simultaneously. external interrupt capability this mode allows the inpu t capture capabilities to be used as external interrupt sources. the inter- rupts are generated on the edge of the articx signal. the edge sensitivity of the external interrupts is programmable (csx bit of articcsr register) and they are independently enabled through ciex bits of the articcsr register. after fetching the interrupt vector, the cfx flags can be read to iden- tify the interrupt source. during halt mode, the external interrupts can be used to wake up the micro (if the ciex bit is set). figure 41. input capture timing diagram 04h counter t 01h f counter xxh 02h 03h 05h 06h 07h 04h articx pin cfx flag icrx register interrupt st72321rx st72321arx st72321jx 65/193 on-chip peripherals (cont?d) 10.3.3 register description control / status register (artcsr) read/write reset value: 0000 0000 (00h) bit 7 = excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock. 1: external clock. bit 6:4 = cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input . bit 3 = tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen). 1: counter running. bit 2 = fcrl force counter re-load this bit is write-only and any attempt to read it will yield a logical zero. when set, it causes the contents of artarr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. bit 1 = oie overflow interrupt enable this bit is set and cleared by software. it allows to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable. 1: overflow interrupt enable. bit 0 = ovf overflow flag this bit is set by hardware and cleared by software reading the artcsr register. it indicates the tran- sition of the counter from ffh to the artarr val- ue . 0: new transition not yet reached 1: transition reached counter access register (artcar) read/write reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] counter access data these bits can be set and cleared either by hard- ware or by software. the artcar register is used to read or write the auto-reload counter ?on the fly? (while it is counting). auto-reload register (artarr) read/write reset value: 0000 0000 (00h) bit 7:0 = ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is au- tomatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register has two pwm management func- tions: ? adjusting the pwm frequency ? setting the pwm duty cycle resolution pwm frequency vs resolution: 70 excl cc2 cc1 cc0 tce fcrl oie ovf f counter with f input =8 mhz cc2 cc1 cc0 f input f input / 2 f input / 4 f input / 8 f input / 16 f input / 32 f input / 64 f input / 128 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 70 ca7ca6ca5ca4ca3ca2ca1ca0 70 ar7ar6ar5ar4ar3ar2ar1ar0 artarr value resolution f pwm min max 0 8-bit ~0.244 khz 31.25 khz [ 0..127 ] > 7-bit ~0.244 khz 62.5 khz [ 128..191 ] > 6-bit ~0.488 khz 125 khz [ 192..223 ] > 5-bit ~0.977 khz 250 khz [ 224..239 ] > 4-bit ~1.953 khz 500 khz st72321rx st72321arx st72321jx 66/193 on-chip peripherals (cont?d) pwm control register (pwmcr) read/write reset value: 0000 0000 (00h) bit 7:4 = oe[3:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels inde- pendently acting on the corresponding i/o pin. 0: pwm output disabled. 1: pwm output enabled. bit 3:0 = op[3:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the four pwm output signals. note : when an opx bit is modified, the pwmx out- put signal polarity is immediately reversed. duty cycle registers (pwmdcrx) read/write reset value: 0000 0000 (00h) bit 7:0 = dc[7:0] duty cycle data these bits are set and cleared by software. a pwmdcrx register is associated with the ocrx register of each pwm channel to determine the second edge location of the pwm signal (the first edge location is common to all channels and given by the artarr register). these pwmdcr regis- ters allow the duty cycle to be set independently for each pwm channel. 70 oe3 oe2 oe1 oe0 op3 op2 op1 op0 pwmx output level opx counter <= ocrx counter > ocrx 100 011 70 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 st72321rx st72321arx st72321jx 67/193 on-chip peripherals (cont?d) input capture control / status register (articcsr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved, always read as 0. bit 5:4 = cs[2:1] capture sensitivity these bits are set and cleared by software. they determine the trigger event polarity on the corre- sponding input capture channel. 0: falling edge triggers capture on channel x. 1: rising edge triggers capture on channel x. bit 3:2 = cie[2:1] capture interrupt enable these bits are set and cleared by software. they enable or disable the input capture channel inter- rupts independently. 0: input capture channel x interrupt disabled. 1: input capture channel x interrupt enabled. bit 1:0 = cf[2:1] capture flag these bits are set by hardware and cleared by software reading the corresponding articrx reg- ister. each cfx bit indicates that an input capture x has occurred. 0: no input capture on channel x. 1: an input capture has occurred on channel x. input capture registers (articrx) read only reset value: 0000 0000 (00h) bit 7:0 = ic[7:0] input capture data these read only bits are set and cleared by hard- ware. an articrx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event. 70 0 0 cs2 cs1 cie2 cie1 cf2 cf1 70 ic7 ic6 ic5 ic4 ic3 ic2 ic1 ic0 st72321rx st72321arx st72321jx 68/193 pwm auto-reload timer (cont?d) table 16. pwm auto-reload timer register map and reset values address (hex.) register label 76543210 0073h pwmdcr3 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0074h pwmdcr2 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0075h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0076h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0077h pwmcr reset value oe3 0 oe2 0 oe1 0 oe0 0 op3 0 op2 0 op1 0 op0 0 0078h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 rie 0 ovf 0 0079h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 007ah artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 007bh articcsr reset value 00 cs2 0 cs1 0 cie2 0 cie1 0 cf2 0 cf1 0 007ch articr1 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 007dh articr2 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 st72321rx st72321arx st72321jx 69/193 10.4 16-bit timer 10.4.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few micros econds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 10.4.2 main features programmable prescaler: f cpu divided by 2, 4 or 8 overflow status flag and maskable interrupt external clock input (must be at least four times slower than the cpu clock speed) with the choice of active edge 1 or 2 output compare functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt 1 or 2 input capture functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 1 . *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be ?1?. 10.4.3 functional description 10.4.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low. counter register (cr): ? counter high register (chr) is the most sig- nificant byte (ms byte). ? counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) ? alternate counter high register (achr) is the m ost significant byte (ms byte). ? alternate counter low r egister (aclr) is the least significant byte (ls byte ). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register , as illustrated in table 1 . the value in the counter register repeats every 131072, 262144 or 524288 cpu clock cycles de- pending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. st72321rx st72321arx st72321jx 70/193 16-bit timer (cont?d) figure 42. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) csr st72321rx st72321arx st72321jx 71/193 16-bit timer (cont?d) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value rema ins unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: ? the tof bit of the sr register is set. ? a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cl eared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 10.4.3.2 external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchron ized with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte st72321rx st72321arx st72321jx 72/193 16-bit timer (cont?d) figure 43. counter timing diagram, internal clock divided by 2 figure 44. counter timing diagram, internal clock divided by 4 figure 45. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 st72321rx st72321arx st72321jx 73/193 16-bit timer (cont?d) 10.4.3.3 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected on the icap i pin (see figure 5 ). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function select the follow- ing in the cr2 register: ? select the timer clock (cc[1:0]) (see table 1 ). ? select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: ? set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull- up without interrupt if this configuration is availa- ble). when an input capture occurs: ? icf i bit is set. ? the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 6 ). ? a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the two input capture functions can be used together even if the timer also uses the two out- put compare functions. 4. in one pulse mode and pwm mode only input capture 2 can be used. 5. the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. moreover if one of the icap i pins is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with interrupt genera- tion in order to measure events that go beyond the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr st72321rx st72321arx st72321jx 74/193 16-bit timer (cont?d) figure 46. input capture block diagram figure 47. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the rising edge is the active edge. st72321rx st72321arx st72321jx 75/193 16-bit timer (cont?d) 10.4.3.4 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16- bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: ? assigns pins with a prog rammable value if the oc i e bit is set ? sets a flag in the status register ? generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: ? set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. ? select the timer clock (cc[1:0]) (see table 1 ). and select the following in the cr1 register: ? select the olvl i bit to applied to the ocmp i pins after the match occurs. ? set the ocie bit to generate an interrupt if it is needed. when a match is found between oc i r register and cr register: ? ocf i bit is set. ? the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). ? a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 1 ) if the timer clock is an external clock, the formula is: where: t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: ? write to the oc i hr register (further compares are inhibited). ? read the sr register (first step of the clearance of the ocf i bit, which may be already set). ? write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr oc i r = t * f cpu presc oc i r = t * f ext st72321rx st72321arx st72321jx 76/193 16-bit timer (cont?d) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. in both internal and external clock modes, ocfi and ocmpi are set while the counter value equals the ocir register value (see fig- ure 8 for an example with f cpu /2 and figure 9 for an example with f cpu /4). this behavior is the same in opm or pwm mode. 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. figure 48. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 st72321rx st72321arx st72321jx 77/193 16-bit timer (cont?d) figure 49. output compare timing diagram, f timer =f cpu /2 figure 50. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf output compare flag i (ocf i ) ocmp i pin (olvl i =1) st72321rx st72321arx st72321jx 78/193 16-bit timer (cont?d) 10.4.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see table 1 ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffc h and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the val- ue fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 1 ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 10 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1 = olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level olvl2 is dedi- cated to the one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72321rx st72321arx st72321jx 79/193 16-bit timer (cont?d) figure 51. one pulse mode timing example figure 52. pulse width modulation mode timi ng example with 2 output compare functions note: on timers with only one output compare register, a fixed frequency pwm signal can be generated using the output compare and the counter overflow to define the pulse length. counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 fffc fffd fffe 2ed0 2ed1 2ed2 st72321rx st72321arx st72321jx 80/193 16-bit timer (cont?d) 10.4.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r regis- ter, and so this functionality can not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values writ- ten in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using the formula in the opposite column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with the oc1r register. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see table 1 ). if olvl1 = 1 and olvl2 = 0 the length of the pos- itive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a cont inuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 1 ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 11 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 st72321rx st72321arx st72321jx 81/193 16-bit timer (cont?d) 10.4.4 low power modes 10.4.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 10.4.6 summary of timer modes 1) see note 4 in section 0.1.3.5 one pulse mode 2) see note 5 in section 0.1.3.5 one pulse mode 3) see note 4 in section 0.1.3.6 pulse width modulation mode mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer regist ers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting re sumes from the previous count when the mcu is woken up by an interrupt with ?e xit from halt mode? capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detecti on circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt wi th ?exit from halt m ode? capability, the icf i bit is set, and the counter value present when exiting fr om halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) one pulse mode no not recommended 1) no partially 2) pwm mode not recommended 3) no st72321rx st72321arx st72321jx 82/193 16-bit timer (cont?d) 10.4.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no succes sful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge tr iggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 st72321rx st72321arx st72321jx 83/193 16-bit timer (cont?d) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer re- mains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer re- mains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 17. clock control bits note : if the external clock pi n is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge tr iggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 1 f cpu / 8 1 0 external clock (where available) 1 st72321rx st72321arx st72321jx 84/193 16-bit timer (cont?d) control/status register (csr) read/write (bits 7:3 read only) reset value: xxxx x0xx (xxh) bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disa- bled the output functions (ocmp1 and ocmp2 pins) to reduce power cons umption. access to the timer registers is still ava ilable, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, mu st be kept cleared. 70 icf1 ocf1 tof icf2 ocf2 timd 0 0 st72321rx st72321arx st72321jx 85/193 16-bit timer (cont?d) input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72321rx st72321arx st72321jx 86/193 16-bit timer (cont?d) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb st72321rx st72321arx st72321jx 87/193 16-bit timer (cont?d) table 18. 16-bit timer register map and reset values related documentation an 973: sci software communications using 16- bit timer an 974: real time clock with st7 timer output compare an 976: driving a buzzer through the st7 timer pwm function an1041: using st7 pwm signal to generate ana- log input (sinusoid) an1046: uart emulation software an1078: pwm duty cycle switch implementing true 0 or 100 per cent duty cycle an1504: starting a pwm signal directly at high level using the st7 16-bit timer address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 x ocf1 x tof x icf2 x ocf2 x timd 0 - x - x timer a: 34 timer b: 44 ic1hr reset value msb xxxxxxx lsb x timer a: 35 timer b: 45 ic1lr reset value msb xxxxxxx lsb x timer a: 36 timer b: 46 oc1hr reset value msb 1000000 lsb 0 timer a: 37 timer b: 47 oc1lr reset value msb 0000000 lsb 0 timer a: 3e timer b: 4e oc2hr reset value msb 1000000 lsb 0 timer a: 3f timer b: 4f oc2lr reset value msb 0000000 lsb 0 timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ic2hr reset value msb xxxxxxx lsb x timer a: 3d timer b: 4d ic2lr reset value msb xxxxxxx lsb x st72321rx st72321arx st72321jx 88/193 10.5 serial peripheral interface (spi) 10.5.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves however the spi interface can not be a master in a multi-master system. 10.5.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.5.3 general description figure 53 shows the serial peripheral interface (spi) block diagram. there are 3 registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through 4 pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and in- put by spi slaves figure 53. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 st72321rx st72321arx st72321jx 89/193 serial peripheral interface (cont?d) ?ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master mcu. 10.5.3.1 functional description a basic example of inte rconnections between a single master and a sing le slave is illustrated in figure 54 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this imp lies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 57 ) but master and slave must be programmed with the same timing mode. figure 54. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software st72321rx st72321arx st72321jx 90/193 serial peripheral interface (cont?d) 10.5.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 56 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 55 ): if cpha=1 (data latched on 2nd clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 10.5.5.3 ). figure 55. generic ss timing diagram figure 56. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin st72321rx st72321arx st72321jx 91/193 serial peripheral interface (cont?d) 10.5.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following steps in order (if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into account) : 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 57 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 10.5.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 10.5.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 57 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section 10.5.3.2 and figure 55 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to enable the spi i/o functions. 10.5.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spics r register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 10.5.5.2 ). st72321rx st72321arx st72321jx 92/193 serial peripheral interface (cont?d) 10.5.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 57 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 57 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 57. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) st72321rx st72321arx st72321jx 93/193 serial peripheral interface (cont?d) 10.5.5 error flags 10.5.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. 10.5.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 10.5.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 10.5.3.2 slave select management . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 58 ). figure 58. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result st72321rx st72321arx st72321jx 94/193 serial peripheral interface (cont?d) 10.5.5.4 single master systems a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 59 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previo us byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. figure 59. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu st72321rx st72321arx st72321jx 95/193 serial peripheral interface (cont?d) 10.5.6 low power modes 10.5.6.1 using the spi to wakeup the mcu from halt mode in slave configuration, the spi is able to wakeup the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is run- ning (interrupt vector fetch). if multiple data trans- fers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. so if slave selec- tion is configured as external (see section 10.5.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 10.5.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the mcu is woken up by an interrupt with ?exit from halt mode? ca- pability. the data received is subsequently read from the spidr r egister when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overru n error is generated. this error can be detected after the fetch of the interrupt routine t hat woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no st72321rx st72321arx st72321jx 96/193 serial peripheral interface (cont?d) 10.5.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1, modf=1 or ovr=1 in the spicsr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.5.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initia lly connected to the ex- ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 19 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 10.5.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 19. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 st72321rx st72321arx st72321jx 97/193 serial peripheral interface (cont?d) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr regist er. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision stat us (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 58 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 10.5.5.2 ). an interrupt is generated if spie = 1 in spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 10.5.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicsr register. this bit is cleared by a software sequence (an ac- cess to the spicr register while modf=1 fol- lowed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 10.5.3.2 slave select management . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will init iate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 53 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0 st72321rx st72321arx st72321jx 98/193 serial peripheral interface (cont?d) table 20. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0 st72321rx st72321arx st72321jx 99/193 10.6 serial communications interface (sci) 10.6.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 10.6.2 main features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver four error detection flags: ? overrun error ? noise error ? frame error ? parity error five interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 10.6.3 general description the interface is externally connected to another device by two pins (see figure 2. ): ? tdo: transmit data output. when the transmit- ter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. ? rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: ? an idle line prior to transmission or reception ? a start bit ? a data word (8 or 9 bits) least significant bit first ? a stop bit indicating that the frame is complete this interface uses two types of baud rate generator: ? a conventional type for commonly-used baud rates ? an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies st72321rx st72321arx st72321jx 100/193 serial communications interface (cont?d) figure 60. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2 st72321rx st72321arx st72321jx 101/193 serial communications interface (cont?d) 10.6.4 functional description the block diagram of the serial control interface, is shown in figure 1. it contains six dedicated reg- isters: ? two control registers (scicr1 & scicr2) ? a status register (scisr) ? a baud rate register (scibrr) ? an extended prescaler receiver register (scier- pr) ? an extended prescaler transmitter register (sci- etpr) refer to the register descriptions in section 0.1.7 for the definitions of each bit. 10.6.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg- ister (see figure 1. ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 61. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame st72321rx st72321arx st72321jx 102/193 serial communications interface (cont?d) 10.6.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be- tween the internal bus and the transmit shift regis- ter (see figure 1. ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scietpr registers. ? set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. ? access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: ? the tdr register is empty. ? the data transfer is beginning. ? the next data can be written in the scidr regis- ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the scidr register places the data di- rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit) the tc bit is set and an interrupt is gener- ated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break frame length depends on the m bit (see figure 2. ). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set, that is, before wr iting the next byte in the scidr. st72321rx st72321arx st72321jx 103/193 serial communications interface (cont?d) 10.6.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be- tween the internal bus and the received shift regis- ter (see figure 1. ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scierpr registers. ? set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: ? the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. ? the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the rdr register as long as the rdrf bit is not cleared. when an overrun error occurs: ? the or bit is set. ? the rdr content is not lost. ? the shift register is overwritten. ? an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the scisr reg- ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge de- tection as well as three valid samples. when noise is detected in a frame: ? the nf flag is set at the rising edge of the rdrf bit. ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read op- eration followed by a scidr register read opera- tion. during reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this frame and the nf flag is set internally (not accessible to the user). this nf flag is accessible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the applica- tion software when the first valid byte is received. see also section 0.1.4.10 . st72321rx st72321arx st72321jx 104/193 serial communications interface (cont?d) figure 62. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register st72321rx st72321arx st72321jx 105/193 serial communications interface (cont?d) framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as th e rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper- ation followed by a scidr register read operation. 10.6.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and re- ceive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 10.6.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry stan dard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 3. the output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divid- ed by a factor ranging from 1 to 255 set in the sci- erpr or the scietpr register. note: the extended prescaler is activated by set- ting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,.. 255 (see scierpr register) 10.6.4.6 receiver muting and wake-up feature in multiprocessor configurat ions it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interr upts are inhibited. a muted receiver may be awakened by one of the following two ways: ? by idle line detection if the wake bit is reset, ? by address mark detectio n if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognized an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution : in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu = 1) and a address mark wake up event occurs (rwu is reset) before the write operation, the rwu bit is set again by this write operation. consequently the address byte is lost and the sci is not woken up from mute mode. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu st72321rx st72321arx st72321jx 106/193 serial communications interface (cont?d) 10.6.4.7 parity control parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in table 1 . table 21. frame formats legend: sb = start bit, stb = stop bit, pb = parity bit note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity: the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in- terface checks if the received data byte has an even number of ?1s? if even parity is selected (ps = 0) or an odd number of ?1s? if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pie is set in the scicr1 register. 10.6.4.8 sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detec- tion, all the three samples should have the same value otherwise the noise flag (nf) is set. for ex- ample: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value is ?1?, but the noise flag bit is set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the de- sired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal sampling clock of the microcon- troller samples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples are at 28s, 32s and 36s respectively (the first sample starting ideally at 0s). but if the falling edge of the internal clock oc- curs just before the pin value changes, the sam- ples would then be out of sync by ~4us. this means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchroniza- tion with the internal sampling clock). m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb | st72321rx st72321arx st72321jx 107/193 serial communications interface (cont?d) 10.6.4.9 clock deviation causes the causes which contribute to the total deviation are: ?d tra : deviation due to transmitter error (local oscillator error of the tr ansmitter or the trans- mitter is transmitting at a different baud rate). ?d quant : error due to the baud rate quantiza- tion of the receiver. ?d rec : deviation of the lo cal oscillator of the receiver: this deviation can occur during the reception of one complete sci message as- suming that the deviation has been compen- sated at the beginning of the message. ?d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% 10.6.4.10 noise error causes see also description of noise error in section 0.1.4.3 . start bit the noise flag (nf) is set during start bit reception if one of the following conditions occurs: 1. a valid falling edge is not detected. a falling edge is considered to be valid if the 3 consecu- tive samples before t he falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits the noise flag (nf) is set during normal data bit re- ception if the following condition occurs: ? during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag getting set. figure 63. bit sampling in reception mode rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 st72321rx st72321arx st72321jx 108/193 serial communications interface (cont?d) 10.6.5 low power modes 10.6.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc regist er is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/re- ceiving until halt mode is exited. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission com- plete tc tcie yes no received data ready to be read rdrf rie yes no overrun error detect- ed or yes no idle line detected idle ilie yes no parity error pe pie yes no st72321rx st72321arx st72321jx 109/193 serial communications interface (cont?d) 10.6.7 register description status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register fol- lowed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data is not transferred to the shift register unless the tdre bit is cleared. bit 6 = tc transmission complete. this bit is set by hardwar e when transmission of a frame containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a pre- amble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not set again until the rdrf bit has been set itself (that is, a new idle line oc- curs). bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf = 1. an interrupt is generat ed if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content is not lost but the shift register is overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be tr ansferred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a parity error oc- curs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an inter- rupt is generated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error 70 tdre tc rdrf idle or nf fe pe st72321rx st72321arx st72321jx 110/193 serial communications interface (cont?d) control register 1 (scicr1) read/write reset value: x000 0000 (x0h) bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m = 1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m = 1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark bit 2 = pce parity control enable. this bit selects the hardware parity control (gener- ation and detection). when the parity control is en- abled, the computed parity is inserted at the msb position (9th bit if m = 1; 8th bit if m = 0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmis- sion). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity is selected after the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled. 70 r8 t8 scid m wake pce ps pie st72321rx st72321arx st72321jx 111/193 serial communications interface (cont?d) control register 2 (scicr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: ? during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. ? when te is set there is a 1 bit-time delay before the transmission starts. caution: the tdo pin is free for general pur- pose i/o only when the te and re bits are both cleared (or if te is never set). bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, otherwise it cannot function in mute mode with wake-up by idle line detection. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter sends a break word at the end of the current word. 70 tie tcie rie ilie te re rwu sbk st72321rx st72321arx st72321jx 112/193 serial communications interface (cont?d) data register (scidr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 1. ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 1. ). baud rate register (scibrr) read/write reset value: 0000 0000 (00h) bits 7:6 = scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bits 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. bits 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate cl ock in conventional baud rate generator mode. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 st72321rx st72321arx st72321jx 113/193 serial communications interface (cont?d) extended receive prescaler division register (scierpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bits 7:0 = erpr[7:0] 8-bit extended receive prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3. ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (scietpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bits 7:0 = etpr[7:0] 8-bit extended transmit prescaler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3. ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 22. baudrate selection 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 symbol parameter conditions standard baud rate unit f cpu accuracy vs standard prescaler f tx f rx communication frequency 8 mhz ~0.16% conventional mode tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 16, pr= 3 tr (or rr)= 2, pr=13 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr)= 1, pr=1 14400 ~14285.71 st72321rx st72321arx st72321jx 114/193 serial communication interface (cont?d) table 23. sci register map and reset values address (hex.) register label 76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 ovr 0 nf 0 fe 0 pe 0 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 0053h scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scierpr reset value msb 0000000 lsb 0 0057h scipetpr reset value msb 0000000 lsb 0 st72321rx st72321arx st72321jx 115/193 10.7 i 2 c bus interface (i2c) 10.7.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, pro- tocol, arbitration and timing. it supports fast i 2 c mode (400khz). 10.7.2 main features parallel-bus/i 2 c protocol converter multi-master capability 7-bit/10-bit addressing smbus v1.1 compliant transmitter/receiver flag end-of-byte transmission flag transfer problem detection i 2 c master features: clock generation i 2 c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation i 2 c slave features: stop bit detection i 2 c bus busy flag detection of misplaced start or stop condition programmable i 2 c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag 10.7.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selectio n is made by soft- ware. mode selection the interface can operate in the four following modes: ? slave transmitter/receiver ? master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master ca- pability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recog- nising its own address (7 or 10-bit), and the gen- eral call address. the ge neral call address de- tection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start con- dition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 64 . figure 64. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b st72321rx st72321arx st72321jx 116/193 i 2 c bus interface (cont?d) acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call ad- dress can be selected by software. the speed of the i 2 c interface may be selected between standard (up to 100khz) and fast i 2 c (up to 400khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 65. i 2 c interface block diagram data register (dr) data shift register comparator own address register 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai own address register 2 (oar2) st72321rx st72321arx st72321jx 117/193 i 2 c bus interface (cont?d) 10.7.4 functional description refer to the cr, sr1 and sr2 registers in section 10.7.7 . for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. 10.7.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: ? acknowledge pulse if the ack bit is set. ? evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister, holding the scl line low (see figure 66 transfer sequencing ev1). next, in 7-bit mode read the dr register to deter- mine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address se- quence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the inter- nal shift register. after each byte the interface gen- erates in sequence: ? acknowledge pulse if the ack bit is set ? evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 66 transfer se- quencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 66 transfer sequencing ev3). when the acknowledge pulse is received: ? the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop con- dition is generated by the master. the interface detects this condition and sets: ? evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 reg- ister (see figure 66 transfer sequencing ev4). error cases ? berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. ? af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. the af bit is cleared by reading the i2csr2 reg- ister. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. soft- ware must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. note : in case of errors, sc l line is not held low; however, the sda line can remain low if the last bits transmitted are all 0. while af=1, the scl line may be held low due to sb or btf flags that are set at the same time. it is then necessary to re- lease both lines by software. st72321rx st72321arx st72321jx 118/193 i 2 c interface (cont?d) how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. smbus compatibility st7 i 2 c is compatible with sm bus v1.1 protocol. it supports all smbus adressing modes, smbus bus protocols and crc-8 packet error checking. refer to an1713: smbus slave driver for st7 i 2 c pe- ripheral. 10.7.4.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condi- tion. once the start condition is sent: ? the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address, holding the scl line low (see figure 66 transfer sequencing ev5). slave address transmission then the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the follow- ing event: ? the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register, holding the scl line low (see figure 66 transfer se- quencing ev9). then the second address byte is sent by the inter- face. after completion of this transfer (and acknowledge from the slave if the ack bit is set): ? the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fig- ure 66 transfer sequencing ev6). next the master must enter receiver or transmit- ter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr reg- ister via the internal shift register. after each byte the interface generates in sequence: ? acknowledge pulse if the ack bit is set ? evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 66 transfer se- quencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. st72321rx st72321arx st72321jx 119/193 i 2 c bus interface (cont?d) master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 66 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: ? evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gener- ate the stop condition. the interface goes auto- matically back to slave mode (m/sl bit cleared). error cases ? berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. note that berr will not be set if an error is de- tected during the first or second pulse of each 9- bit transaction: single master mode if a start or stop is issued during the first or sec- ond pulse of a 9-bit transaction, the berr flag will not be set and trans fer will continue however the busy flag will be reset. to work around this, slave devices should issue a nack when they receive a misplaced start or stop. the reception of a nack or busy by the master in the middle of communication gives th e possibility to reiniti- ate transmission. multimaster mode normally the berr bit would be set whenever unauthorized transmission takes place while transfer is already in progress. however, an is- sue will arise if an external master gen erates an unauthorized start or stop while the i 2 c master is on the first or second pulse of a 9-bit transac- tion. it is possible to wo rk around this by polling the busy bit during i 2 c master mode transmis- sion. the resetting of the busy bit can then be handled in a similar manner as the berr flag being set. ? af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. the af bit is cleared by reading the i2csr2 reg- ister. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. soft- ware must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. ? arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note : in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then neces- sary to release both lines by software. st72321rx st72321arx st72321jx 120/193 i 2 c bus interface (cont?d) figure 66. transfer sequencing legend: s=start, sr = repeated start, p=st op, a=acknowledge, na=non-acknowledge, evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev3: evf=1, btf=1, cleared by reading sr1 re gister followed by writing dr register. ev3-1: evf=1, af=1, btf=1; af is cleared by readi ng sr1 register. btf is cleared by releasing the lines (stop=1, stop=0) or by writing dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading sr2 register. ev5: evf=1, sb=1, cleared by reading sr1 regi ster followed by writing dr register. ev6: evf=1, cleared by reading sr 1 register followed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev8: evf=1, btf=1, cleared by reading sr1 re gister followed by writing dr register. ev9: evf=1, add10=1, cleared by reading sr1 r egister followed by wr iting dr register. 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter 10-bit master receiver: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a .... . datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7 st72321rx st72321arx st72321jx 121/193 i 2 c bus interface (cont?d) 10.7.5 low power modes 10.7.6 interrupts figure 67. event flags and interrupt generation note : the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc reg- ister is reset (rim instruction). mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an in terrupt with ?exit from halt mode? capability. interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite yes no end of byte transfer event btf yes no address matched event (slave mode) adsel yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multima ster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10 st72321rx st72321arx st72321jx 122/193 i 2 c bus interface (cont?d) 10.7.7 register description i 2 c control register (cr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes: ? when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 ? when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. ? to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). the 00h general call address is ac- knowledged (01h ignored). 0: general call disabled 1: general call enabled note: in accordance with the i2c standard, when gcal addressing is enabl ed, an i2c slave can only receive data. it will not transmit data to the master. bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). ? in master mode: 0: no start generation 1: repeated start generation ? in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). ? in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. ? in slave mode: 0: no stop generation 1: release the scl and sda lines after the cur- rent byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 67 for the relationship between the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 66 ) is de- tected. 70 0 0 pe engc start ack stop ite st72321rx st72321arx st72321jx 123/193 i 2 c bus interface (cont?d) i 2 c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described in figure 66 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: ? btf=1 (byte received or transmitted) ? adsl=1 (address matched in slave mode while ack=1) ? sb=1 (start condition generated in master mode) ? af=1 (no acknowledge received after byte transmission) ? stopf=1 (stop condition detected in slave mode) ? arlo=1 (arbitration lost in master mode) ? berr=1 (bus error, misplaced start or stop condition detected) ? add10=1 (master has sent header byte) ? address byte successfully transmitted in mas- ter mode. bit 6 = add10 10-bit addressing in master mode . this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the pe- ripheral is disabled (pe=0). 0: no add10 event occurred. 1: master has sent first address byte (header) bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after de- tection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disa- bled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. the busy flag of the i2csr1 register is cleared if a bus error occurs. 0: no communication on the bus 1: communication ongoing on the bus note: ? the busy flag is not updated when the inter- face is disabled (pe=0) . this can have conse- quences when operating in multimaster mode; i.e. a second active i 2 c master commencing a transfer with an unset busy bit can cause a con- flict resulting in lost dat a. a software workaround consists of checking that the i 2 c is not busy be- fore enabling the i 2 c multimaster cell. bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). ? following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 66 ). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. ? following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register con- tent or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software read- ing sr1 register or by hardware when the inter- face is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched 70 evf add10 tra busy btf adsl m/sl sb st72321rx st72321arx st72321jx 124/193 i 2 c bus interface (cont?d) bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated i 2 c status register 2 (sr2) read only reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interfac e is disabled (pe=0). the scl line is not held low while af=1 but by oth- er flags (sb or btf) that are set at the same time. 0: no acknowledge failure 1: acknowledge failure note: ? when an af event occurs, the scl line is not held low; however, the sda line can remain low if the last bits transmitted are all 0. it is then nec- essary to release both lines by software. bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interfac e is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardwa re when the interface los- es the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by soft- ware reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected note: ? in a multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the acknowledge bit. mishandling of the arlo bit from the i2csr2 register may occur when a sec- ond master simultaneou sly requests the same data from the same slave and the i 2 c master does not acknowledge the data. the arlo bit is then left at 0 instead of being set. bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a misplaced start or stop condition. an inter- rupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the in- terface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition note: ? if a bus error occurs, a stop or a repeated start condition should be generated by the master to re-synchronize communication, get the transmis- sion acknowledged and the bus released for fur- ther communication bit 0 = gcal general call (slave mode). this bit is set by hardwa re when a general call ad- dress is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 70 0 0 0 af stopf arlo berr gcal st72321rx st72321arx st72321jx 125/193 i 2 c bus interface (cont?d) i 2 c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc[6:0] 7-bit clock divider. these bits select the speed of the bus (f scl ) de- pending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). refer to the electrical characteristics section for the table of values. note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register ( dr) read / write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] 8-bit data register. these bits contain the byte to be received or trans- mitted on the bus. ? transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. ? receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the following data bytes are received one by one after reading the dr register. 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0 st72321rx st72321arx st72321jx 126/193 i 2 c bus interface (cont?d) i 2 c own address register (oar1) read / write reset value: 0000 0000 (00h) 7-bit addressing mode bit 7:1 = add[7:1] interface address . these bits define the i 2 c bus address of the inter- face. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is don?t care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 10-bit addressing mode bit 7:0 = add[7:0] interface address . these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). i 2 c own address register (oar2) read / write reset value: 0100 0000 (40h) bit 7:6 = fr[1:0] frequency bits. these bits are set by software only when the inter- face is disabled (pe=0). to configure the interface to i 2 c specified delays select the value corre- sponding to the microcontroller frequency f cpu . bit 5:3 = reserved bit 2:1 = add[9:8] interface address . these are the most significant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. 70 add7 add6 add5 add4 add3 add2 add1 add0 70 fr1 fr0 0 0 0 add9 add8 0 f cpu fr1 fr0 < 6 mhz 0 0 6 to 8 mhz 0 1 st72321rx st72321arx st72321jx 127/193 i2c bus interface (cont?d) table 24. i 2 c register map and reset values address (hex.) register label 765 4 3210 0018h i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 0019h i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 001ah i2csr2 reset value 0 0 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 001bh i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 001ch i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 001dh i2coar2 reset value fr1 0 fr0 1000 add9 0 add8 00 001eh i2cdr reset value msb 000 0 000 lsb 0 st72321rx st72321arx st72321jx 128/193 10.8 10-bit a/d converter (adc) 10.8.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 10.8.2 main features 10-bit conversion up to 16 channels with multiplexed input linear successive approximation data register (dr) which contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 68 . figure 68. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 div 4 f adc f cpu d1 d0 adcdrl 0 1 00 00 00 ch3 div 2 st72321rx st72321arx st72321jx 129/193 10-bit a/d converter (adc) (cont?d) 10.8.3 functional description the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v aref (high-level voltage reference) then the conversion result is ffh in the a dcdrh register and 03h in the adcdrl register (with out overflow indication). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrh and ad- cdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 10.8.3.1 a/d converter configuration the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the cs[3:0] bits to assign the analog channel to convert. 10.8.3.2 starting the conversion in the adccsr register: ? set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? the result is in the adcdr registers. a read to the adcdrh or a write to any bit of the adccsr register resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrl register 3. read the adcdrh register. this clears eoc automatically. note: the data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion re- sult. to read only 8 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrh register. this clears eoc automatically. 10.8.3.3 changing the conversion channel the application can change channels during con- version. when software modifies the ch[3:0] bits in the adccsr register, the current conversion is stopped, the eoc bit is cleared, and the a/d con- verter starts converting the newly selected chan- nel. 10.8.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions. 10.8.5 interrupts none. mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. st72321rx st72321arx st72321jx 130/193 10-bit a/d converter (adc) (cont?d) 10.8.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by hard- ware when software reads the adcdrh register or writes to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. 0: f adc = f cpu /4 1: f adc = f cpu /2 bit 5 = adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion bit 4 = reserved. must be kept cleared. bit 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *the number of channels is device dependent. refer to the device pinout description. data register (adcdrh) read only reset value: 0000 0000 (00h) bit 7:0 = d[9:2] msb of converted analog value data register (adcdrl) read only reset value: 0000 0000 (00h) bit 7:2 = reserved. forced by hardware to 0. bit 1:0 = d[1:0] lsb of converted analog value 70 eoc speed adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 000 ain1 0 001 ain2 0 010 ain3 0 011 ain4 0 100 ain5 0 101 ain6 0 110 ain7 0 111 ain8 1 000 ain9 1 001 ain10 1 010 ain11 1 011 ain12 1 100 ain13 1 101 ain14 1 110 ain15 1 111 70 d9 d8 d7 d6 d5 d4 d3 d2 70 000000d1d0 st72321rx st72321arx st72321jx 131/193 10-bit a/d converter (cont?d) table 25. adc register map and reset values address (hex.) register label 76543210 0070h adccsr reset value eoc 0 speed 0 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 0071h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0072h adcdrl reset value000000 d1 0 d0 0 st72321rx st72321arx st72321jx 132/193 11 instruction set 11.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in seven main groups: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two submodes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 26. cpu addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([ $10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btj t $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10] ,#7,skip 00..ff 00..ff byte + 3 st72321rx st72321arx st72321jx 133/193 instruction set overview (cont?d) 11.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 11.1.2 immediate immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. 11.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, t hus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 11.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three submodes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 11.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two submodes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations st72321rx st72321arx st72321jx 134/193 instruction set overview (cont?d) 11.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 27. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 11.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative st72321rx st72321arx st72321jx 135/193 instruction set overview (cont?d) 11.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in the following table: using a prebyte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf st72321rx st72321arx st72321jx 136/193 instruction set overview (cont?d) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > st72321rx st72321arx st72321jx 137/193 instruction set overview (cont?d) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z st72321rx st72321arx st72321jx 138/193 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 12.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v.they are given only as de- sign guidelines and are not tested. 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 69 . figure 69. pin loading conditions 12.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 70 . figure 70. pin input voltage c l st7 pin v in st7 pin st72321rx st72321arx st72321jx 139/193 12.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 voltage characteristics 12.2.2 current characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an uni ntentional internal reset is generated or an unexpected change of the i/o configuration occurs (for exampl e, due to a corrupt ed program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for reset , 10k for i/os). for the same reason, unused i/ o pins must not be directly tied to v dd or v ss . 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72321rx st72321arx st72321jx 141/193 operating conditions (cont?d) 12.3.2 operating condi tions with low voltage detector (lvd) subject to general operating conditions for v dd , f cpu , and t a . notes: 1. data based on characterization results, tested in production for rom devices only. 2. if the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. below 3.8v, device operation is not guaranteed. 3. data based on characterization results, not tested in production. 3. when vt por is faster than 100 s/v, the reset signal is released af ter a delay of max. 42s after v dd crosses the v it+(lvd) threshold. 12.3.3 auxiliary voltage detector (avd) thresholds subject to general operating conditions for v dd , f cpu , and t a . 1. data based on characterization results, tested in production for rom devices only. 12.3.4 external voltage detector (evd) thresholds subject to general operating conditions for v dd , f cpu , and t a . 1. data based on characterization results, not tested in production. symbol parameter conditions min typ max unit v it+(lvd) reset release threshold (v dd rise) vd level = high in option byte 4.0 1) 4.2 4.5 v vd level = med. in option byte 2) vd level = low in option byte 2) 3.55 1) 2.95 1) 3.75 3.15 4.0 1) 3.35 1) v it-(lvd) reset generation threshold (v dd fall) vd level = high in option byte 3.8 4.0 4.25 1) vd level = med. in option byte 2) vd level = low in option byte 2) 3.35 1) 2.8 1) 3.55 3.0 3.75 1)) 3.15 1) v hys(lvd) lvd voltage threshold hysteresis v it+(lvd) -v it-(lvd) 200 mv vt por v dd rise time 3)2) lvd enabled 6 s/v 100ms/v t g(vdd) v dd glitches filtered (not detect- ed) by lvd 3) 40 ns symbol parameter conditions min typ max unit v it+(avd) 1 ? 0 avdf flag toggle threshold (v dd rise) vd level = high in option byte 4.4 1) 4.6 4.9 1) v vd level = med. in option byte vd level = low in option byte 3.95 1) 3.4 1) 4.15 3.6 4.4 1) 3.8 1) v it-(avd) 0 ? 1 avdf flag toggle threshold (v dd fall) vd level = high in option byte 4.2 1) 4.4 4.65 1) vd level = med. in option byte vd level = low in option byte 3.75 1) 3.2 1) 4.0 3.4 4.2 1) 3.6 1) v hys(avd) avd voltage threshold hysteresis v it+(avd) -v it-(avd) 200 mv v it- voltage drop between avd flag set and lvd reset activated v it-(avd) -v it-(lvd) 450 mv symbol parameter conditions min typ max unit v it+(evd) 1 ? 0 avdf flag toggle threshold (v dd rise) 1) 1.15 1.26 1.35 v v it-(evd) 0 ? 1 avdf flag toggle threshold (v dd fall) 1) 1.1 1.2 1.3 v hys(evd) evd voltage threshold hysteresis v it+(evd) -v it-(evd) 200 mv st72321rx st72321arx st72321jx 142/193 12.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consump- tion, the two current values must be added (except for halt mode for which the clock is stopped). 12.4.1 current consumption notes: 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - program executed from ram, cpu running with ram access. the increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - lvd disabled. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source ( section 12.4.2 ) and the peripheral power consumption ( section 12.4.3 ). 3. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or vss (no load), lvd disabled. data based on characterization result s, tested in production at v dd max. and f cpu max. 4. data based on characterisation results, not tested in pr oduction. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load); clock input (osc1) driven by external square wave , lvd disabled. to obtain the total current consumption of the devic e, add the clock source consumption ( section 12.4.2 ). symbol parameter conditions flash devices rom devices unit typ max 1) typ max 1) i dd supply current in run mode 2) f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 1.3 2.0 3.6 7.1 2.0 3.0 5.0 10.0 ma supply current in slow mode 2) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 600 700 800 1100 2700 3000 3600 4000 600 700 800 1100 1800 2100 2400 3000 a supply current in wait mode 2) f osc =2mhz, f cpu =1mhz f osc =4mhz, f cpu =2mhz f osc =8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1.0 1.5 2.5 4.5 3.0 4.0 5.0 7.0 1.0 1.5 2.5 4.5 1.3 2.0 3.3 6.0 ma supply current in slow wait mode 2) f osc =2mhz, f cpu =62.5khz f osc =4mhz, f cpu =125khz f osc =8mhz, f cpu =250khz f osc =16mhz, f cpu =500khz 580 650 770 1050 1200 1300 1800 2000 70 100 200 350 200 300 600 1200 a supply current in halt mode 3) -40c t a +85c <1 10 <1 10 a -40c t a +125c <1 50 <1 50 i dd supply current in active-halt mode 4) f osc =2mhz f osc =4mhz f osc =8mhz f osc =16mhz 80 160 325 650 no max. guaran- teed 80 160 325 650 no max. guar- anteed a st72321rx st72321arx st72321jx 143/193 supply current characteristics (cont?d) 12.4.1.1 power consumption vs f cpu : flash devices figure 72. typical i dd in run mode figure 73. typical i dd in slow mode figure 74. typical i dd in wait mode figure 75. typ. i dd in slow-wait mode 0 1 2 3 4 5 6 7 8 9 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 8mhz 4mhz 2mhz 1mhz 0.00 0.20 0.40 0.60 0.80 1.00 1.20 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 500khz 250khz 125khz 62.5khz 0 1 2 3 4 5 6 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) idd (ma) 8mhz 4mhz 2mhz 1mhz 0.00 0.20 0.40 0.60 0.80 1.00 1.20 3.2 3.6 4 4.4 4.8 5.2 5.5 vdd (v) () 500khz 250khz 125khz 62.5khz st72321rx st72321arx st72321jx 144/193 supply current characteristics (cont?d) 12.4.2 supply and clock managers the previous current consumption specified for t he st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consump- tion, the two current values must be added (except for halt mode). notes: 1.. data based on characterization results done with the external components specified in section 12.5.3 , not tested in production. 2. as the oscillator is based on a current sour ce, the consumption does not depend on the voltage. symbol parameter conditions typ max unit i dd(rcint) supply current of inte rnal rc oscillator 625 a i dd(res) supply current of re sonator oscillator 1) & 2) see section 12.5.3 on page 147 i dd(pll) pll supply current v dd = 5v 360 i dd(lvd) lvd supply current v dd = 5v 150 300 st72321rx st72321arx st72321jx 145/193 supply current characteristics (cont?d) 12.4.3 on-chip peripherals measured on lqfp64 generic board t a = 25c f cpu =4mhz. notes: 1. data based on a differential i dd measurement between reset configur ation (timer count er running at f cpu /4) and timer counter stopped (only ti md bit set). data valid for one timer. 2. data based on a differential i dd measurement between reset configuration (timer st opped) and timer counter enabled (only tce bit set). 3. data based on a differential i dd measurement between reset configuration (spi disabled) and a permanent spi master communication at maximum speed (data sent equal to 55h).t his measurement includes the pad toggling consumption. 4. data based on a differential i dd measurement between sci low power state (scid=1) and a permanent sci data trans- mit sequence. 5. data based on a differential i dd measurement between reset c onfiguration (i2c disabled) and a permanent i2c master communication at 100khz (data sent equal to 55h). this measurement include the pad t oggling consumption (27kohm external pull-up on clock and data lines). 6. data based on a differential i dd measurement between reset configur ation and continuous a/d conversions. symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 1) v dd = 5.0v 50 a i dd(art) art pwm supply current 2) v dd = 5.0v 75 a i dd(spi) spi supply current 3) v dd = 5.0v 400 a i dd(sci) sci supply current 4) v dd = 5.0v 400 a i dd(i2c) i2c supply current 5) v dd = 5.0v 175 a i dd(adc) adc supply current when converting 6) v dd = 5.0v 400 a st72321rx st72321arx st72321jx 146/193 12.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 12.5.1 general timings 12.5.2 external clock source figure 76. typical application with an external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. t c(inst) is the number of t cpu cycles needed to finish the current instru ction execution. 3. data based on design simulation and/or technol ogy characteristics, not tested in production. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2312t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = t c(inst) + 10 10 22 t cpu f cpu =8mhz 1.25 2.75 s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 76 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 5 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l osc1 input leakage current v ss v in v dd 1 a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% st72321rx st72321arx st72321jx 147/193 clock and timing characteristics (cont?d) 12.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph is based on characterization results with specified typical ex- ternal components. in the application, the resona- tor and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distorti on and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). notes: 1. the oscillator selection can be opt imized in terms of supply current usi ng an high quality resonat or with small r s value. refer to crystal/ceramic resonator manufacturer for more details. 2. data based on characterisation results, not tested in production. symbol parameter conditions min max unit f osc oscillator frequency 1) lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor 2) 20 40 k c l1 c l2 recommended load capacitance ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) r s =200 lp oscillator r s =200 mp oscillator r s =200 ms oscillator r s =100 hs oscillator 22 22 18 15 56 46 33 33 pf symbol parameter conditions typ max unit i 2 osc2 driving current v dd =5v lp oscillator v in =v ss mp oscillator ms oscillator hs oscillator 80 160 310 610 150 250 460 910 a st72321rx st72321arx st72321jx 148/193 figure 77. typical application with a crystal or ceramic resonator figure 78 . application with a crystal or ceramic resonator for rom (lqfp64 or any 48/60k rom) 1 osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors st72321rx st72321arx st72321jx 149/193 clock and timing characteristics (cont?d) notes: 1. resonator characteristics given by the ceramic resonator manufacturer. 2. smd = [-r0: plastic tape package ( ? =180mm), -b0: bulk] lead = [-a0: flat pack package (r adial taping ho= 18mm), -b0: bulk] 3. lp mode is not recommended for 2 mhz resonator bec ause the peak to peak amplitude is too small (>0.8v) for more information on these resonat ors, please consult www.murata.com supplier f osc (mhz) typical ceramic resonators 1) reference 2) recommended oscrange option bit configuration murata 2 cstcc2m00g56a-r0 mp mode 3) 4 cstcr4m00g55b-r0 ms mode 8 cstce8m00g55a-r0 hs mode 16 cstce16m0g53a-r0 hs mode st72321rx st72321arx st72321jx 150/193 clock characteristics (cont?d) 12.5.4 rc oscillators figure 79. typical f osc(rcint) vs t a note: to reduce disturbance to the rc oscillator, it is recommended to place decoupling capacitors between v dd and v ss as shown in figure 99 symbol parameter conditions min typ max unit f osc (rcint) internal rc oscillator frequency see figure 79 t a =25c, v dd =5v 23.55.6mhz 3 3.2 3.4 3.6 3.8 4 -45 0 25 70 130 t a (c) f osc(rcint) (mhz) vdd = 5v vdd = 5.5v st72321rx st72321arx st72321jx 151/193 clock characteristics (cont?d) note: 1. data based on characterization results. 12.5.5 pll characteristics note: 1. data characterized but not tested. the user must take the pll jitter into account in the application (for example in serial communication or sampling of high frequency signals). the pll jitter is a periodic effect, which is integrated over several cpu cycles. therefore the lo nger the period of the application sign al, the less it will be impacted by the pll jitter. figure 80 shows the pll jitter integrated on application signals in the range 125khz to 4mhz. at frequen- cies of less than 125khz, the jitter is negligible. figure 80. integrated pll jitter vs signal frequency 1 note 1: measurement conditions: f cpu = 8mhz. symbol parameter conditions min typ max unit f osc pll input frequency range 2 4 mhz f cpu / f cpu instantaneous pll jitter 1) f osc = 4 mhz. 1.0 2.5 % f osc = 2 mhz. 2.5 4.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 4 mhz 2 mhz 1 mhz 500 khz 250 khz application frequency +/-jitter (%) st72321rx st72321arx st72321jx 152/193 12.6 memory characteristics 12.6.1 ram and hardware registers 12.6.2 flash memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). not tested in production. 2. data based on characterization results, not tested in production. 3. v pp must be applied only during the programming or erasi ng operation and not permanently for reliability reasons. 4. data based on simulation re sults, not tested in production. warning: do not connect 12v to v pp before v dd is powered on, as this may damage the device. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v dual voltage hdflash memory symbol parameter conditions min 2) typ max 2) unit f cpu operating frequency read mode 0 8 mhz write / erase mode 1 8 v pp programming voltage 3) 4.5v v dd 5.5v 11.4 12.6 v i dd supply current 4) run mode (f cpu = 4mhz) 3 ma write / erase 0 power down mode / halt 1 10 a i pp v pp current 4) read (v pp =12v) 200 write / erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention t a =85c 40 years t a = 105c 15 t a = 125c 7 n rw write erase cycles t a = 55c 1000 cycles t a = 85c 100 cycles t prog t erase programming or erasing tempera- ture range -40 25 85 c st72321rx st72321arx st72321jx 153/193 12.7 emc characteristics susceptibility tests are pe rformed on a sample ba- sis during product characterization. 12.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 12.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance flash device: v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 4b rom device: v dd = 5v, t a = +25c, f osc = 8 mhz, conforms to iec 1000-4-2 4a v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a func- tional disturbance v dd = 5v, t a = +25c, f osc = 8 mhz, con- forms to iec 1000-4-4 3b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a func- tional disturbance v dd = 5v, t a = +25c, f osc = 8 mhz, con- forms to iec 1000-4-4 3b st72321rx st72321arx st72321jx 154/193 emc characteristics (cont?d) 12.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. notes: 1. data based on characterization results, not tested in production. 2. refer to application note an1709 for data on other package types. symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] 1 unit 8/4mhz 16/8mhz s emi peak level v dd = 5v, t a = +25c, lqfp64 10x10 package conforming to sae j 1752/3 0.1mhz to 30mhz 15 20 db v 30mhz to 130mhz 20 27 130mhz to 1ghz 7 12 sae emi level 2.5 3 - s emi peak level 60k rom devices: v dd = 5v, t a = +25c, lqfp64 package conforming to sae j 1752/3 0.1mhz to 30mhz 15 20 db v 30mhz to 130mhz 20 27 130mhz to 1ghz 7 12 sae emi level 2.5 3 - s emi peak level 8/16/32k rom devices: v dd = 5v, t a = +25c, lqfp44 10x10 package conforming to sae j 1752/3 0.1mhz to 30mhz 17 21 db v 30mhz to 130mhz 24 30 130mhz to 1ghz 18 23 sae emi level 3 3.5 - st72321rx st72321arx st72321jx 155/193 emc characteristics (cont?d) 12.7.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitiv ity. for more details, re- fer to the application note an1181. 12.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test con- forms to the jesd22-a114a/a115a standard. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. 12.7.3.2 static latch-up lu : 2 complementary static tests are required on 6 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. electrical sensitivities symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c 200 symbol parameter conditions class 1) lu static latch-up class t a = +125c conforming to jesd 78 ii level a st72321rx st72321arx st72321jx 156/193 12.8 i/o port pin characteristics 12.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 81. unused i/os configured as input figure 82. typical i pu vs. v dd with v in =v ss notes: 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt tr igger switching levels. based on c haracterization results, not tested. 3. when the current limitation is not possible, the v in maximum must be respected, otherwise refer to i inj(pin) specifica- tion. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72321rx st72321arx st72321jx 158/193 i/o port pin characteristics (cont?d) figure 86. typical v ol vs. v dd (standard) figure 87. typical v ol vs. v dd (high-sink) figure 88. typical v dd -v oh vs. v dd 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=5ma ta= -4 5c ta= 25c ta= 95c ta= 140 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=2ma ta=-45c ta=25c ta=95c ta=140c 0 0.1 0.2 0.3 0.4 0.5 0.6 22.533.544.555.56 vdd(v) vol(v) at iio=8ma ta= 140c ta=95c ta=25c ta=-45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 22.533.544.555.56 v dd(v ) vol(v) at iio=20ma ta = 140 c ta =95 c ta =25 c ta =-45c 0 1 2 3 4 5 6 22.533.544.555.56 vdd(v) vdd-voh(v) at iio=-5m a ta= -45c ta= 25c ta= 95c ta= 140c 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vdd-voh(v) at iio=-2ma ta= -45c ta= 25c ta= 95c ta= 140c st72321rx st72321arx st72321jx 159/193 12.9 control pin characteristics 12.9.1 asynchronous reset pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmit t trigger switching levels. 3. the i io current sunk must always respect t he absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 4. to guarantee the reset of the device, a mi nimum pulse has to be applied to the reset pin. all short pulses applied on the reset pin with a duration below t h(rstl)in can be ignored. 5. the reset network (the resistor and tw o capacitors) protects the device against parasitic resets, especially in noisy en- vironments. 6. data guaranteed by design, not tested in production. symbol parameter conditions min typ max unit v il input low level voltage 1) 0.16xv dd v v ih input high level voltage 1) 0.85xv dd v hys schmitt trigger voltage hysteresis 2) 2.5 v v ol output low level voltage 3) v dd =5v i io =+2ma 0.2 0.5 i io input current on reset pin 2 ma r on weak pull-up equival ent resistor 20 30 120 k t w(rstl)out generated reset pulse duration stretch applied on external pulse 042 6) s internal reset sources 20 30 42 6) s t h(rstl)in external reset pulse hold time 4) 2.5 s t g(rstl)in filtered glitch duration 5) 200 ns st72321rx st72321arx st72321jx 160/193 control pin characteristics (cont?d) figure 89. reset pin protection when lvd is enabled. 1)2)3)4) figure 90. reset pin protection when lvd is disabled. 1) note 1: ? the reset network protects the device against parasitic resets. ? the output of the external reset circuit must have an open- drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). ? whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.9.1 on page 159 . otherwise the reset will not be taken into account internally. ? because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must en- sure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 12.2.2 on page 139 . note 2: when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to fi lter noise on the reset line. note 3: in case a capacitive power supply is used, it is recommended to connect a 1m pull-down resistor to the reset pin to discharge any residual voltage induc ed by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). note 4: tips when using the lvd: ? 1. check that all recommendations related to reset circuit have been applied (see notes above). ? 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m pull-down on the reset pin. ? 3. the capacitors connected on the reset pin and also the power supply are key to avoi d any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. otherwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor. 0.01 f st72xxx pulse generator filter r on v dd watchdog lvd reset internal reset reset external required 1m optional (note 3) 0.01 f external reset circuit user required st72xxx pulse generator filter r on v dd watchdog internal reset st72321rx st72321arx st72321jx 161/193 control pin characteristics (cont?d) 12.9.2 iccsel/v pp pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 91. two typical applications with iccsel/v pp pin 2) notes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. when icc mode is not required by the application iccsel/v pp pin must be tied to v ss . symbol parameter conditions min max 1 unit v il input low level voltage 1) flash versions v ss 0.2 v rom versions v ss 0.3xv dd v ih input high level voltage 1) flash versions v dd -0.1 12.6 rom versions 0.7xv dd v dd i l input leakage current v in =v ss 1 a iccsel/v pp st72xxx 10k programming tool v pp st72xxx st72321rx st72321arx st72321jx 162/193 12.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (out- put compare, input capture, external clock, pwm output...). 12.10.1 8-bit pwm-art auto-reload timer 12.10.2 16-bit timer symbol parameter conditions min typ max unit t res(pwm) pwm resolution time 1t cpu f cpu =8mhz 125 ns f ext art external clock frequency 0 f cpu /2 mhz f pwm pwm repetition rate 0 f cpu /2 res pwm pwm resolution 8bit v os pwm/dac output step voltage v dd =5v, res=8-bits 20 mv symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit st72321rx st72321arx st72321jx 163/193 12.11 communication interface characteristics 12.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 92. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or charac terisation results, not tested in production. 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 4. depends on f cpu . for example, if f cpu = 8 mhz, then t cpu = 1 / f cpu = 125 ns and t su(ss ) = 175 ns. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time 4) slave t cpu + 50 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (after enable edge) 120 t cpu t h(mo) data output hold time 0 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in st72321rx st72321arx st72321jx 164/193 communication interface characteristics (cont?d) figure 93. spi slave timing diagram with cpha=1 1) figure 94. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the dat a output line of the spi (mosi in mast er mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=1 mosi input miso output cpha=1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha = 0 mosi output miso input cpha = 0 cpha = 1 cpha = 1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) msb in msb out bit6 in bit6 out lsb out lsb in seenote2 seenote2 cpol = 0 cpol = 1 cpol = 0 cpol = 1 t r(sck) t f(sck) t h(mo) t v(mo) st72321rx st72321arx st72321jx 165/193 communication interface characteristics (cont?d) 12.11.2 i 2 c - inter ic control interface subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table. figure 95. typical application with i 2 c bus and timing diagram 4) notes: 1. data based on standard i 2 c protocol requirement, not tested in production. 2. the device must internally provide a hold time of at least 300ns for the sd a signal in order to bridge the undefined region of the falling edge of scl. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 4. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 5. at 4mhz f cpu , max.i 2 c speed (400khz) is not achievable. in this case, max. i 2 c speed will be approximately 260khz. symbol parameter standard mode i 2 c fast mode i 2 c 5) unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda sck 4.7k sdai st72xxx scli v dd 100 100 v dd 4.7k i 2 cbus st72321rx st72321arx st72321jx 166/193 communication interface characteristics (cont?d) the following table gives the values to be written in the i2cccr register to obtain the required i 2 c scl line frequency. table 28. scl frequency table legend: r p = external pull-up resistance f scl = i 2 c speed na = not achievable note: ? for speeds around 200 khz, achieved speed can have 5% tolerance ? for other speed ranges, achieved speed can have 2% tolerance the above variations depend on the accuracy of the external components used. f scl (khz) i2cccr value f cpu =4 mhz. f cpu =8 mhz. v dd = 4.1 v v dd = 5 v v dd = 4.1 v v dd = 5 v r p =3.3k r p =4.7k r p =3.3k r p =4.7k r p =3.3k r p =4.7k r p =3.3k r p =4.7k 400 na na na na 83h 83 83h 83h 300 na na na na 85h 85h 85h 85h 200 83h 83h 83h 83h 8ah 89h 8ah 8ah 100 10h 10h 10h 10h 24h 23h 24h 23h 50 24h 24h 24h 24h 4ch 4ch 4ch 4ch 20 5fh 5fh 5fh 5fh ffh ffh ffh ffh st72321rx st72321arx st72321jx 167/193 12.12 10-bit adc characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. any added external serial resist or will downgrade the adc accuracy (es pecially for resistance greater than 10k ). data based on characterization resu lts, not tested in production. 2. injecting negative current on any of t he analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. analog pins can be protect ed against negative injection by adding a schottky diode (pin to ground). injecting negative current on di gital input pins degrades adc accuracy especially if performed on a pin close to the analog input pins. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 12.8 does not affect the adc accuracy. symbol parameter conditions min typ max unit f adc adc clock frequency 0.4 2 mhz v aref analog reference voltage 0.7*v dd v aref v dd 3.8 v dd v v ain conversion voltage range 1) v ssa v aref r ain external input impedance see figure 96 and figure 97 k c ain external capacitor on analog input pf f ain variation freq. of analog input signal hz c adc internal sample and hold capacitor 12 pf t adc conversion time (sample+hold) f cpu =8mhz, speed=0 f adc =2mhz 7.5 s t adc - no of sample capacitor loading cycles - no. of hold conversion cycles 4 11 1/f adc st72321rx st72321arx st72321jx 168/193 adc characteristics (cont?d) figure 96. r ain max. vs f adc with c ain =0pf 1) figure 97. recommended c ain & r ain values. 2) figure 98. typical a/d converter application notes: 1. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad ca- pacitance (3pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 2. this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decreased to allow the use of a larger serial resistor (r ain) . 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 2 mhz 1 mhz 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i l 1 a v t 0.6v v t 0.6v c adc 12pf v ain r ain 10-bit a/d conversion 2k ( max ) c ain st72321rx st72321arx st72321jx 169/193 adc characteristics (cont?d) 12.12.1 analog power supply and reference pins depending on the mcu pin count, the package may feature separate v aref and v ssa analog power supply pins. these pi ns supply power to the a/d converter cell and function as the high and low reference voltages for the conversion. separation of the digital and analog power pins al- low board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see section 12.12.2 general pcb design guidelines ). 12.12.2 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to sh ield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. ? use separate digital and analog planes. the an- alog ground plane should be connected to the digital ground plane via a single point on the pcb. ? filter power to the analog power planes. it is rec- ommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and optionally, if needed 10pf capacitors as close as possible to the st7 power supply pins and a 1 to 10f ca- pacitor close to the power source (see figure 99 ). ? the analog and digital power supplies should be connected in a star network. do not use a resis- tor, as v aref is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. ? properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital out- puts on the same i/o port as the a/d input being converted. figure 99. power supply filtering v ss v dd v dd st72xxx v aref v ssa power supply source st7 digital noise filtering external noise filtering 1 to 10 f 0.1 f 0.1 f st72321rx st72321arx st72321jx 170/193 10-bit adc characteristics (cont?d) 12.12.3 adc accuracy conditions: v dd =5v 1) notes: 1. adc accuracy vs. negative injection current: injecting negative current may reduce the accuracy of the conversion being performed on anot her analog input. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 12.8 does not affect the adc accuracy. 2. data based on characterization results, monitored in production to guarantee 99.73% with in max value from -40c to 125c ( 3 distribution limits). figure 100. adc accuracy characteristics symbol parameter conditions typ max 2) unit |e t | total unadjusted error 1) 34 lsb |e o | offset error 1) 23 |e g | gain error 1) 0.5 3 |e d | differential linearity error 1) cpu in run mode @ f adc 2 mhz. 12 |e l | integral linearity error 1) cpu in run mode @ f adc 2 mhz. 12 e o e g 1lsb ideal 1lsb ideal v aref v ssa ? 1024 -------------------------------------------- = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v aref v ssa st72321rx st72321arx st72321jx 171/193 13 package characteristics 13.1 package mechanical data figure 101. 64-pin low profile quad flat package (14x14) figure 102. 64-pin low profile quad flat package (10 x10) dim. mm inches 1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 16.00 0.6299 d1 14.00 0.5512 e 16.00 0.6299 e1 14.00 0.5512 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n 64 note 1. values in inches are converted from mm and rounded to 4 decimal digits. c h l l1 e b a a1 a2 e e1 d d1 dim. mm inches 1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n 64 note 1. values in inches are converted from mm and rounded to 4 decimal digits. a a2 a1 c l1 l e e1 d d1 e b st72321rx st72321arx st72321jx 172/193 package mechanical data ( cont?d ) figure 103. 44-pin low profile quad flat package figure 104. 32-pin low profile quad flat package - dim. mm inches 1) note 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n 44 a a2 a1 b e l1 l h c e e1 d d1 dim. mm inches 1) note 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n 32 h c l l1 b e a1 a2 a e e1 d d1 st72321rx st72321arx st72321jx 173/193 13.2 thermal characteristics notes: 1. the maximum chip-junction temperatur e is based on technology characteristics. 2. the maximum power dissipation is obtained from the formula pd = (tj -ta) / rthja. the power dissipation of an application can be defined by the user with the fo rmula: pd=pint+pport where pint is the chip internal power (iddxvdd) and pport is the por t power dissipation depending on t he ports used in the applica- tion. symbol ratings value unit r thja package thermal resistance (junction to ambient) lqfp64 14x14 lqfp64 10x10 lqfp44 10x10 47 50 52 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c st72321rx st72321arx st72321jx 174/193 13.3 soldering and glueability information refer to jedec specification jstd020d for a de- scription of the recommended reflow oven profile for these packages. in order to meet environmental requirements, st offers this device in different grades of eco- pack ? packages, depending on their level of en- vironmental compliance. ecopack ? specifica- tions, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. recommended glue for smd plastic packages dedicated to molding co mpound with silicone: heraeus: pd945, pd955 loctite: 3615, 3298 st72321rx st72321arx st72321jx 175/193 14 st72321 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom/fastrom). st72321 devices are rom versions. st72p321 devices are factory advanced service technique rom (fastrom) versions: they are factory-pro- grammed hdflash devices. flash devices are shipped to customers with a default content, while rom/fastrom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the cus- tomer using the option bytes while the rom/fas- trom devices are factory-configured. 14.1 flash option bytes the option bytes allow the hardware configuration of the microcontroller to be selected. they have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 programming tool). the default con- tent of the flash is fixed to ffh. to program the flash devices directly using icp, flash devices are shipped to customers with the internal rc clock source enabled. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). option byte 0 opt7= wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt6= wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt5 = reserved, must be kept at default value. opt4:3= vd[1:0] voltage detection these option bits enable the voltage detection block (lvd, and avd) with a selected threshold for the lvd and avd (evd+avd). caution: if the medium or low thresholds are se- lected, the detection may occur outside the speci- fied operating voltage range. below 3.8v, device operation is not guaranteed. for details on the avd and lvd threshold levels refer to section 12.3.2 on page 141 opt2 = reserved, must be kept at default value. opt1= pkg0 package selection bit 0 this option bit isused with the pkg1 bit to select the package. static option byte 0 70 static option byte 1 70 wdg reserved vd reserved pkg0 fmp_r pkg1 rstc osctype oscrange plloff halt sw 10 10 2 10 default111001111 1 10 1 1 1 1 selected low voltage detector vd1 vd0 lvd and avd off 1 1 lowest threshold: (v dd ~3v) 1 0 med. threshold (v dd ~3.5v) 0 1 highest threshold (v dd ~4v) 0 0 st72321rx st72321arx st72321jx 176/193 st72321 device configuratio n and ordering information (cont?d) opt0= fmp_r flash memory read-out protection read-out protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. erasing the option bytes when the fmp_r option is selected causes the whole user memory to be erased first, and the device can be reprogrammed. refer to section 4.3.1 and the st7 flash pro- gramming reference manual for more details. note: readout protection is not supported if lvd is enabled. 0: read-out protection enabled 1: read-out protection disabled option byte 1 opt7= pkg1 package selection bit 1 this option bit selects the package. note: on the chip, each i/o port has up to 8 pads. pads that are not bonded to external pins are forced in input pull-up co nfiguration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. are in input floating configuration after reset. refer to note 4 on page 13 . opt6 = rstc reset clock cycle selection this option bit selects the number of cpu cycles applied during the reset ph ase and when exiting halt mode. for resonator o scillators, it is advised to select 4096 due to th e long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles opt5:4 = osctype[1:0] oscillator type these option bits select the st7 main clock source type. opt3:1 = oscrange[2:0] oscillator range when the resonator oscilla tor type is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. otherwise, these bits are used to select the normal operating frequency range. opt0 = plloff pll activation this option bit activates the pll which allows mul- tiplication by two of the main input clock frequency. the pll is guaranteed only with an input frequen- cy between 2 and 4mhz, for this reason the pll must not be used with the internal rc oscillator. 0: pll x2 enabled 1: pll x2 disabled caution : the pll can be enabled only if the ?osc range? (opt3:1) bits are configured to ? 2~4mhz?. otherwise, the device functionality is not guaranteed. version selected package pkg 1 pkg 0 (a)r lqfp64 1 0 jlqfp4400 clock source osctype 10 resonator oscillator 0 0 reserved 0 1 internal rc oscillator 1 0 external source 1 1 typ. freq. range oscrange 210 1~2mhz 0 0 0 2~4mhz 0 0 1 4~8mhz 0 1 0 8~16mhz 0 1 1 st72321rx st72321arx st72321jx 177/193 st72321 device configuratio n and ordering information (cont?d) 14.2 device ordering informat ion and transfer of customer code customer code is made up of the rom/fas- trom contents and the list of the selected options (if any). the rom/fastrom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the develop- ment tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide de- tailed information on contractual points. caution: the readout protection binary value is inverted between rom and flash products. the option byte checksum will differ between rom and flash. st72321rx st72321arx st72321jx 178/193 figure 105. ordering information scheme st72 f 321 j 7 t 8 family st7 microcontroller family memory type f: flash blank : rom p = fastrom memory size 6 = 32k 7 = 48k 9 = 60k package t = lqfp example: no. of pins j = 44 or 42 ar = 64 (lqfp64 10x10 package) r = 64 (lqfp64 14x14 package) sub-family 325 temperature range 3 = -40 to 125 c 6 = -40 c to 85 c for a list of available options (e.g. memory size, pac kage) and orderable part numbers or for further information on any aspect of this device, please cont act the st sales office nearest to you. st72321rx st72321arx st72321jx 179/193 st723251 device configuration a nd ordering information (cont?d) figure 106. rom factory coded device types device package version xxx / code name (defined by stmicroelectronics) 3 = standard -40 to +125 c 6= standard -40 to +85 c t= plastic thin quad flat pack st72321ar9, st72321ar7, st72321ar6, st72321r9, st72321r7, st72321r6 st72321j9, st72321j7 st72321rx st72321arx st72321jx 180/193 st72321 device configuratio n and ordering information (cont?d) st72321 microcontroller option list (last update mar 2009) customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* :. . . . . . . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): ----------------------|----------------|---------------------------------- rom device: | 60k | 48k | 32k | ----------------------|----------------|---------------------------------- lqfp44 10x10: |[ ] st72321j9 |[ ] st72321j7 |[ ] see note 1 | lqfp64 14x14: |[ ] st72321r9 |[ ] st72321r7 |[ ] st72321r6 | lqfp64 10x10: |[ ] st72321ar9 |[ ] st72321ar7 |[ ] st72321ar6 | ----------------------|----------------|---------------------------------- die form: | 60k | 48k | 32k | ----------------------|----------------|---------------------------------- 64-pin: | [ ] | [ ] | [ ] | conditioning (check only one option) : --------------------------------|----------------------------------------- packaged product | die product (dice tested at 25c only) | --------------------------------|----------------------------------------- [ ] tape & reel [ ] tray |[ ] tape & reel |[ ] inked wafer |[ ] sawn wafer on sticky foil version/temp. range (do not check for die product):please refer to datasheet for specific sales conditions : standard [ ] -40 to +85c [ ] -40 to +125c special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max) authorized characters are letters, digits, '.', '-', '/' and spaces only. clock source selection: [ ] resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] internal rc (4) [ ] external clock pll (3) [ ] disabled [ ] enabled css (5) [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] high threshold [ ] med.threshold [ ] low threshold reset delay [ ] 256 cycles [ ] 4096 cycles watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt [ ] reset [ ] no reset readout protection(2): [ ] disabled [ ] enabled date . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . note 1 : configure 44-pin/32k devices using separate st72321b option list. note 2 : readout protection is not supported if lvd is enabled. note 3 : pll must not be enabled if internal rc network or external clock is selected. note 4 : internal rc can only be used if lvd is enabled. note 5 : device operation below 3.8v not guaranteed st72321rx st72321arx st72321jx 181/193 device configuration an d ordering information (cont?d) 14.3 development tools development tools for the st7 microcontrollers in- clude a complete range of hardware systems and software tools from stmicroelectronics and third- party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers. 14.3.1 starter kits st offers complete, affordable starter kits . starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your applica- tion. 14.3.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assem- bler-linker toolchain, which are all seamlessly in- tegrated in the st7 integrated development envi- ronments in order to facilitate the debugging and fine-tuning of your application. the cosmic c compiler is available in a free version that outputs up to 16kbytes of code. the range of hardware tools includes full-featured st7-emu3 series emulators and the low-cost rlink in-circuit debugger/programmer. these tools are supported by the st7 toolset from st- microelectronics, which in cludes the stvd7 inte- grated development environment (ide) with high- level language debugger, editor, project manager and integrated programming interface. 14.3.3 programming tools during the development cycle, the st7-emu3 se- ries emulators and the rlink provide in-circuit programming capability fo r programming the flash microcontroller on your application board. st also provides a low- cost dedicated in-circuit programmer, the st7-stick , as well as st7 socket boards which provide all the sockets re- quired for programming any of the devices in a specific st7 sub-family on a platform that can be used with any tool with in-circuit programming ca- pability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solu- tions, which are ready to integrate into your pro- duction environment. evaluation boards three different evaluation boards are available: st7232x-eval st72f321 /324/521 evaluation board, with icc connector for programming capability. provides di rect connection to st7- dvp3 emulator. supplied with daughter boards (core module) for st72f321, st72324 & st72f521. st7mdt20-evc/ xx 1 with cab lqfp64 14x14 socket st7mdt20-evy/ xx 1 with yamaichi lqfp64 10x10 socket table 29. stmicroelectronics development tools note 1: add suffix /eu, /uk, /us for the power supply of your region. supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe & t.e.b. st72321ar, st72f321ar st7mdt20-dvp3 st7mdt20-t6a/ dvp st7mdt20m- emu3 st7mdt20m-teb st7sb20m/xx 1 st72321r, st72f321r st7mdt20-t64/ dvp st72321j, st72f321j st7mdt20-t44/ dvp st7mdt20j- emu3 st7mdt20j-teb st7sb20j/xx 1 st72321rx st72321arx st72321jx 182/193 device configuration an d ordering information (cont?d) table 30. suggested list of socket types 14.3.4 socket and emulator adapter information for information on the type of socket that is sup- plied with the emulator, refer to the suggested list of sockets in table 30 . note: before designing the board layout, it is rec- ommended to check the overall dimensions of the socket as they may be greater than the dimen- sions of the device. for footprint and other mechanical information about these sockets and adapters, refer to the manufacturer?s datasheet. related documentation an 978: st7 visual develop software key debug- ging features an 1938: st7 visual develop for st7 cosmic c toolset users an 1940: st7 visual develop for st7 assembler linker toolset users device socket (supplied with st7mdt20m- emu3) emulator adapter (supplied with st7mdt20m-emu3) lqfp64 14 x14 cab 3303262 cab 3303351 lqfp64 10 x10 yamaichi ic149-064-*75-*5 yamaichi icp-064-6 lqfp44 10 x10 yamaichi ic149-044-*52-*5 yamaichi icp-044-5 st72321rx st72321arx st72321jx 183/193 14.4 st7 application notes table 31. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative in- put voltages example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16-bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art st72321rx st72321arx st72321jx 184/193 an1947 st7mc pmac sine wave motor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits vs industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscilla- tor an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an1039 st7 math utility routines table 31. st7 application notes identification description st72321rx st72321arx st72321jx 185/193 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug an st72324 target application an1477 emulated data eeprom with xflash memory an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma-delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 31. st7 application notes identification description st72321rx st72321arx st72321jx 186/193 15 known limitations 15.1 all flash and rom devices 15.1.1 external rc option the external rc clock source option described in previous datasheet revisi ons is no longer support- ed and has been removed from this specification. 15.1.2 safe connection of osc1/osc2 pins the osc1 and/or osc2 pins must not be left un- connected otherwise the st7 main oscillator may start and, in this configuration, could generate an f osc clock frequency in excess of the allowed maximum (>16mhz.), putting the st7 in an un- safe/undefined state. refer to section 6.2 on page 25 . 15.1.3 reset pin protec tion with lvd enabled as mentioned in note 2 below figure 89 on page 160 , when the lvd is enabled, it is recommended not to connect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to filter noise on the reset line. 15.1.4 unexpected reset fetch if an interrupt request occurs while a ?pop cc? in- struction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the reset vector address to the cpu. workaround to solve this issue, a ?pop cc? instruction must always be preceded by a ?sim? instruction. 15.1.5 external interrupt missed to avoid any risk if generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either ddr and or. any input signal edge during this period will not be detected and will no t generate an interrupt. this case can typically oc cur if the application re- freshes the port configuration registers at intervals during runtime. workaround the workaround is based on software checking the level on the interrupt pin before and after writ- ing to the pxor or pxddr registers. if there is a level change (depending on the sensitivity pro- grammed for this pin) the interrupt routine is in- voked using the call instruction with three extra push instructions before executing the interrupt routine (this is to make the call compatible with the iret instruction at the end of the interrupt service routine). but detection of the level change does not make sure that edge occurs during the critical 1 cycle du- ration and the interrupt has been missed. this may lead to occurrence of same interrupt twice (one hardware and another with software call). to avoid this, a semaphore is set to '1' before checking the level change. the semaphore is changed to level '0' inside the interrupt routine. when a level change is detected, the semaphore status is checked and if it is '1' this means that the last interrupt has been missed. in this case, the in- terrupt routine is invoked with the call instruction. there is another possible case i.e. if writing to pxor or pxddr is done wi th global interrupts dis- abled (interrupt mask bit set). in this case, the semaphore is changed to '1' when the level change is detected. detecting a missed interrupt is done after the global interrupts are enabled (inter- rupt mask bit reset) and by checking the status of the semaphore. if it is '1' this means that the last interrupt was missed and th e interrupt routine is in- voked with the call instruction. to implement the workaround, the following soft- ware sequence is to be followed for writing into the pxor/pxddr registers. the example is for for port pf1 with falling edge interrupt sensitivity. the software sequence is given for both cases (global interrupt disabled/enabled). case 1: writing to pxor or pxddr with global in- terrupts enabled: ld a,#01 ld sema,a ; set the semaphore to '1' ld a,pfdr and a,#02 ld x,a ; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a ; write to pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#02 ld y,a ; store the level after writing to pxor/pxddr ld a,x ; check for falling edge cp a,#02 jrne out st72321rx st72321arx st72321jx 187/193 tnz y jrne out ld a,sema ; check the semaphore status if edge is detected cp a,#01 jrne out call call_routine; call the interrupt routine out:ld a,#00 ld sema,a .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#00 ld sema,a iret case 2: writing to pxor or pxddr with global in- terrupts disabled: sim ; set the interrupt mask ld a,pfdr and a,#$02 ld x,a ; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a; write into pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#$02 ld y,a ; store the level after writing to pxor/ pxddr ld a,x ; check for falling edge cp a,#$02 jrne out tnz y jrne out ld a,#$01 ld sema,a ; set the semaphore to '1' if edge is detected rim ; reset the interrupt mask ld a,sema ; check the semaphore status cp a,#$01 jrne out call call_routine; call the interrupt routine rim out: rim jp while_loop .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#$00 ld sema,a iret 15.1.6 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. note: clearing the related in terrupt mask will not generate an unwanted reset concurrent interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: ? the interrupt flag is cleared within its own inter- rupt routine ? the interrupt flag is cleared within any interrupt routine ? the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following se- quence: perform sim and rim operation before and after resetting an active interrupt request. example: sim reset interrupt flag rim nested interrupt context: the symptom does not occur when the interrupts are handled normally, i.e. when: ? the interrupt flag is cleared within its own inter- rupt routine st72321rx st72321arx st72321jx 188/193 ? the interrupt flag is cleared within any interrupt routine with higher or identical priority level ? the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following se- quence: push cc sim reset interrupt flag pop cc st72321rx st72321arx st72321jx 189/193 known limitations (cont?d) 15.1.7 sci wrong break duration description a single break character is sent by setting and re- setting the sbk bit in th e scicr2 register. in some cases, the break character may have a long- er duration than expected: - 20 bits instead of 10 bits if m=0 - 22 bits instead of 11 bits if m=1. in the same way, as lo ng as the sbk bit is set, break characters are sent to the tdo pin. this may lead to generate one break more than expect- ed. occurrence the occurrence of the problem is random and pro- portional to the baudrate. with a transmit frequen- cy of 19200 baud (f cpu =8mhz and sci- brr=0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with the communication protocol in the application, soft- ware can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the applica- tion is not doing anything between the idle and the break. this can be ensured by temporarily disa- bling interrupts. the exact sequence is: - disable interrupts - reset and set te (idle request) - set and reset sbk (break request) - re-enable interrupts 15.1.8 16-bit timer pwm mode in pwm mode, the first pwm pulse is missed after writing the value fffch in the oc1r register (oc1hr, oc1lr). it leads to either full or no pwm during a period, depending on the olvl1 and olvl2 settings. 15.1.9 timd set simultaneously with oc interrupt if the 16-bit timer is disabled at the same time the output compare event occurs then output compare flag gets locked and cannot be cleared before the timer is enabled again. impact on the application if output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. consequently the interrupt serv- ice routine is ca lled repeatedly. workaround disable the timer interrupt before disabling the tim- er. again while enabling, first enable the timer then the timer interrupts. perform the following to disable the timer: tacr1 or tbcr1 = 0x00h; // disable the com- pare interrupt tacsr | or tbcsr | = 0x40; // disable the timer perform the following to enable the timer again: tacsr & or tbcsr &= ~0x40; // enable the tim- er tacr1 or tbcr1 = 0x40; // enable the compare interrupt 15.1.10 i2c multimaster in multimaster configurat ions, if the st7 i2c re- ceives a start condition from another i2c mas- ter after the start bit is set in the i2ccr register and before the start condition is generated by the st7 i2c, it may ignore the start condition from the other i2c master. in this case, the st7 master will receive a nack from the other device. on reception of the nack, st7 can send a re-start and slave address to re-initiate communication 15.2 all flash devices 15.2.1 internal rc oscillator with lvd the internal rc can only be used if lvd is ena- bled. 15.3 limitations specific to rev q and rev s flash devices 15.3.1 adc accuracy the improved adc accuracy specifications given in section 12.12.3 do not apply to rev q and rev s devices. their accuracy remains as specified in the previous datasheet revision and summarized in the table below. symbol parameter typ max unit |e t | total unadjusted error 46 lsb |e o | offset error 35 |e g | gain error 0.5 4.5 |e d | differential linearity error 1.5 4.5 |e l | integral linearity er- ror 1.5 4.5 st72321rx st72321arx st72321jx 190/193 to identify these parts, check the internal sales type on the box label or the trace code marking on the package. 15.4 limitations specific to rom devices 15.4.1 lvd operation depending on the operating conditions, especially the v dd ramp up speed and ambient temperature, in some cases the lvd may not start. when this occurs, the mcu may operate outside the guaran- teed functional area (see datasheet figure 76) without being forced into reset state. in this case, proper use of the watchdog may make it possible to recover through a watchdog re- set and allow normal operations to resume. consequently, the lvd function is not guaranteed in the current silicon revisi on. for complete securi- ty, an external reset circuit must be added. rev internal salestype trace code rev q 72f321xxx$a2 72f321xxx$u2 813xxxq 813xxxq rev s 72f321xxx$a8 72f321xxx$u8 813xxxs 813xxxs rev 9 (full spec) 72f321xxx$a3 72f321xxx$u3 813xxx9 813xxx9 st72321rx st72321arx st72321jx 191/193 15.4.2 lvd startup behaviour when the lvd is enabled, the mcu reaches its authorized operating voltage from a reset state. however, in some devices, the reset state is re- leased when vdd is approximately between 0.8v and 1.5v. as a consequence, the i/os may toggle when vdd is within this window. this may be an issue especially for applications where the mcu drives power components. figure 107. lvd startup behaviour 15.4.3 avd not supported on some devices with a specific v dd ramp up speed the avd may not start. as a result it cannot generate interrupts when v dd rises and falls. 15.4.4 internal rc oscillator operation internal rc oscillator oper ation is not supported in rom devices. 15.4.5 external clock source with pll external clock source is not supported with the pll enabled. 15.4.6 pull-up not present on pe2 unlike st72f321 flash devices, st72321 rom devices have no weak pull-up on port pe2. in lqfp44 rom devices, the pe2 pad is not con- nected to an internal pull-up like other unbonded pads (see note 4 under table 2, ?device pin de- scription,? on page 10). it is recommended to con- figure it as output push pull to avoid added current consumption. 15.4.7 read-out protection with lvd the lvd is not supported if readout protection is enabled. 15.4.8 safe connection of osc1/osc2 pins the osc1 and/or osc2 pins must not be left un- connected otherwise the st 7 main oscillator may start and, in this configuration, could generate an f osc clock frequency in excess of the allowed maximum (>16mhz.), putting the st7 in an un- safe/undefined state. refer to section 6.2 on page 25 . 5v 1.5v v it+ 0.8v lvd reset v d d window t st72321rx st72321arx st72321jx 192/193 16 revision history table 32. revision history date revision description of changes 18-oct-2004 1.10 added ?related documentation? section in specific chapters throughout document flash readout protection sentence added section 4.3.1 on page 18 i 2 c chapter updated, ( section 10.7 ) vt por max modified in section 12.4 on page 142 added figure 89 on page 160 modified description of t w(rstl)out in ?asynchronous reset pin? on page 159 added note on pe2 pin in table 2, ?device pin description,? on page 10 modified v aref min in ?10-bit adc characteristics? on page 167 modified i inj for pc6 in section 12.8 updated adc accuracy data and notes in section 12.12.3 on page 170 and ?known lim- itations? on page 186 added ?clearing active interrupts out side interrupt routine? on page 187 i2c multimaster bug added in known limitations, section 15.1.10 please read carefully the ?known limitations? on page 186 13-mar-2009 2 updated root part numbers and device summary table on coverpage. removed temperature ranges 1, 5, and 7. renamed all tqfp packages, lqfp. updated note 6 below table 2, ?dev ice pin description,? on page 10. updated data retention in ?features? and section 12.6.2 flash memory . updated figure 50 ?output compare timing diagram, ftimer = fcpu/4? . updated figure 94 ?spi master timing diagram 1)? . added section 10.8.3.3 ?changing t he conversion channel? on page 129 . modified ?absolute maximum ratings (electrical sensitivity)? on page 155 . update note 4 in section 12.8 i/o port pin characteristics ?general characteris- tics? . updated notes in section 13.2 thermal characteristics . removed recommended wave soldering profile and recommended reflow soldering oven profile, and added ecopack text in ?soldering and glueability information? on page 174 ( section 13.3 ). removed automotive temperature ranges from section 12.3.1 general operating condi- tions , and from figure 106 ?rom factory coded device ty pes? and option list. modified section 14.2 ?device ordering information and transfer of customer code? on page 177: replace list or order c odes by ordering scheme. added section 15.1.5 exter nal interrupt missed , and section 15.2.1 internal rc oscillator with lvd in section 15 known limitations . modified section 15.1.9 ?timd set simulta- neously with oc interrupt? on page 189. st72321rx st72321arx st72321jx 193/193 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in mi litary, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
Price & Availability of ST72321AR6T6XXX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |